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Place & Route with FinFETs and Double Patterning

Place & Route with FinFETs and Double Patterning
by Paul McLellan on 09-29-2014 at 8:00 am

 Place & route in the 16/14nm era requires a new approach since it is significantly more complex. Of course, every process generation is more complex than the one before and the designs are bigger. But modern processes have new problems. The two biggest changes are FinFETs and double patterning.

FinFETs, as I assume you know, are vertical transistors that stick up like a shark’s fin from the wafer and then the gate is wrapped around them on 3 sides. The gate width is quantized, meaning you can have 2, 3 or more FinFETs to make up what in a planar process would be a single transistor. The FinFETs thus end up being laied out in a grid. There are a lot of complications to laying out FinFET cells but place & route doesn’t have to deal with that since the standard cell library is an input file. However, the FinFET architecture makes for dense cells which can lead to difficulty in finding points to pick up signals. Also, while FinFETs are lower leakage they have relatively high dynamic power which can lead to power/timing closure difficulties.

Double patterning comes about because we are still stuck with 193nm light for lithography which only allows us to get down to about 80nm pitch. To go lower, as we must for processes at 20nm and below, we have to print half the polygons using one mask, and half using another, so that neither mask violates the 80nm pitch rule but together the two masks generate all the polygons. The most common way to do this is called LELE (litho-etch-litho-etch) although there are other potential approaches. LELE is the cheapest approach but the two masks are not self-aligned so there is increased process variation depending on how accurate the alignment of the masks turns out to be.

The problem with double patterning is that it is possible to design layouts that cannot be split into two masks. This will happen if there is an “odd cycle” in the design where polygon A is close to B (so must be colored differently) and a third polygon C is close to both A and B and so cannot be colored with either of the only two colors we have. This can require either adjusting the layout and moving the polygons, or alternatively a polygon can often be split into two with the two halves being colored differently and overlapping when manufactured.

To make things worse, this is not a local phenomenon. The odd cycle can be a large (odd) number of polygons spread all over a chip or a large block, as in the diagram above. Place & route needs to be double patterning aware to minimize the problems that it creates, but also to locate and correct any odd cycles that are generated.

 The introduction of both multi-patterning and FinFETs has a huge impact on all the key engines in the place and route flow. The complexity and number of DRC rules along with the multi-patterning rules has increased significantly and poses a big challenge to the router. Tighter design rules and FinFET process requirements, such as voltage threshold-aware spacing, implant layer rules, etc., impose restrictions on placement, floorplanning, and optimization engines that directly impacts design utilization and area. Multi-patterning closure and timing closure are inter-dependent, each requiring minimal design perturbations and can increase design closure time. In order to account for multi-patterning and FinFETs, the entire place and route flow needs to be completely revamped.

Olympus-SoC provides a comprehensive multi-patterning place and route platform to address the challenges of advanced nodes. It addresses all the routing rules required for 14/16/20nm, including dealing with the interactions between multi-patterning and FinFETs. The routing engine provides complete support for DRC/multi-patterning rules for the leading foundries. The Olympus-SoC database is architected to handle the requirements for multiple masks and supports anchoring and propagation of pre-colored objects. All the key engines in the entire flow, including placement, optimization, timing, and extraction are FinFET and multi-patterning aware. Tight integration with Calibre ensures sign-off clean physical verification with minimal design iterations.

Mentor has a white paper FinFET and Multi-patterning Aware Place and Route Implementation. You can find it here.

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