So what comes after FinFETs? At 14/16nm (or 22nm if you are Intel) we had FinFET transistors, where the channel was no longer planar but stuck out of the wafer vertically, and the gate wrapped around it on 3 sides. The key thing that made FinFET transistors attractive was that the channel was thin so that the gate controlled it well. FD-SOI has the same attraction, although with a totally different topology. By building the channel on top of an insulator, it was thin and well-controlled. So is it FinFETs all the way down to 10nm, 7nm 5nm, how low can you go limbo dancing?
At the imec day at Semicon West a month ago, An Steegen told us what they thought. She is the senior vice president of process technology there and when she talks…well, water and fire-hoses come to mind.
Nanowires are the first thing to think about. Instead of having the gate wrapped around 3 sides of the channel, how about 4. The channel is basically a wire running through the gate. Is that better than a fin? Imec has studied it. 10nm turns out to be the FinFET scaling limit and at 7nm three nanowires running through the gate is the best solution.
So what you are probably thinking of is a vertical gate of some sort with some silicon nanowires running through. But maybe not. Making the whole structure vertical, so that the source and drain are above each other with the gate in between. The idea is to make the transistor smaller areally and make it take up less space for the source/drain contacts to the metal fabric above. At these dimensions wiring resistance is a huge problem too, so short wires are doubly attractive.
Alternatives are to enhance the effectiveness of the transistor. That means adding new materials to it such as strained germanium Pfets and III/V Nfets. Using new (well, old familiar favorites) to make the channel. Vdd can be lower but channel mobility higher.
These approaches are still CMOS, even if not clearly recognizable. But research is going on in even more esoteric approaches. Have you heard of magnetic tunnel junctions (MTJ). Yeah, me neither until An told me. Spin Wave. Spin Torque majority voting. Plasmonics. Lots to learn about still!
Then there is all the stuff about getting optical onto the chip. Or making 3D (TSV) really work.Share this post via: