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Electronic Design Automation
As 2D device scaling becomes impractical, 3D-IC integration is emerging as the natural evolution of semiconductor technology; it is the convergence of performance, power and functionality. Some of the benefits of 3D-IC, such as increasing complexity, improved performance, reducing power consumption and decreasing footprints,… Read More
If you are in Asia then the Synopsys user group SNUG is coming up, soon in Japan and next month in China. Actually if you are in India I’m afraid you already missed it last month, just after DAC.
SNUG Japan is on 12th July in a couple of days time from 10am until 8pm in Tokyo.
In China there are 3 between August 14th and 21st
In Mike Muller’s keynote at DAC he wanted to make formal approaches an integral part of writing RTL. After all, formal captures design intent and then, at least much of the time, can verify whether the RTL written actually matches that intent. Today, formal is not used that way and is typically something served “on the side” by specialist… Read More
SPICE circuit simulation is used for transistor-level analysis while Place and Route tools are typically used to connect cells and blocks of an SoC, so why would there be a connection between these two EDA tools?
I read a press release today from ATopTech and Berkeley Design Automation that talked about how SPICE and P&R are … Read More
See how Synopsys’ advanced analog verification solution can dramatically increase your verification productivity with CustomExplorer Ultra, along with CustomSim and CustomSim-VCS. CustomExplorer Ultra is a comprehensive simulation and debug environment for analog and mixed-signal design verification.
Web … Read More
First, I must say that I’m biased. I like Cheerleaders, they are lots of fun, I even married one. Second, I’m not a fan of Peggy Aycinena. She has been on her EDA feminist rant for years now and I have been targeted multiple times. My solution has been to ignore her and any publication that supports her but this time she has gone too far.… Read More
If you are involved in testing memory or logic of ARM-based designs, you’ll want to attend this free seminar on July 17, 2012 in Santa Clara. Mentor Graphics and ARM have a long standing partnership, and have optimized the Mentor test products (a.k.a Tessent) for the ARM processors and memory IP.
The lunch seminar runs from 10:30-1:00… Read More
Next week it is Semicon West in the Moscone Center from Tuesday to Thursday, July 10-12th. Cadence will be on a panel session during a session entitled The 2.5D and 3D packaging landscape for 2015 and beyond. This starts with 3 short keynotes:
In my circuit design past I did DRAM work at Intel, so I was interested in learning more about Novocell Semiconductor and their design of One Time Programmable (OTP) IP. Walter Novosell is the President/CTO of Novocell and talked with me by phone on Thursday.… Read More
At DAC in June I didn’t get a chance to visit ClioSoft for a product update so instead I read their white paper this week, “The Power of Visual Diff for Schematics & Layouts“. My background is transistor-level IC design so anything with schematics is familiar and interesting.
The Challenge
Hand-crafted … Read More
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