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May 26, 2020April 26, 2022

Effect of Design on Transistor Density

Effect of Design on Transistor Density
by Scotten Jones on 05-26-2020 at 10:00 am
Categories: Semiconductor Services, TechInsights, TSMC
4 Comments

I have written a lot of articles looking at leading edge processes and comparing the process density. One comment I often get are that the process density numbers I present do not correlate with the actual transistor density on released products. A lot of people want to draw conclusions an Intel’s processes versus TSMC’s processes based on Apple cell phone application processors versus Intel microprocessors, this is not a valid comparison! In this article I will review the metrics I use for transistor density and why I use them and why comparing transistor density on product designs is not valid.

The first comment I want to make is that I am not a circuit designer and therefore I am not familiar with all of the aspects of the decisions that go into creating a design that may impact the transistor density of the final product, but I do have an understanding of the difference in density that can occur across a given process.

Logic designs are made up of standard cells and the size of the standard cells is driven by 4 parameters, metal two pitch (M2P), track height (TH), contacted poly pitch (CPP) and single diffusion break (SDB) versus double diffusion break (DDB).

Cell Height
The height of a standard cell is the metal two pitch (M2P) multiplied by the number of tracks (Track Height or TH). In recent years in order to continue to shrink standard cells the TH has been reduced while simultaneously reducing M2P as part of something called design technology co-optimization (DTCO). One key aspect of reducing TH is that the number of fins per transistor must be reduced at low THs due to space constraints, this is called fin depopulation. If you reduce the number of fins per transistor you get less drive current from each transistor unless you do something else to compensate for it such as increasing fin height, therefore DTCO.

Cell Width
The width of a standard cell depends on contacted poly pitch (CPP), whether the process supports single diffusion break (SDB) or double diffusion break (DDB) and the type of cell. For example, a NAND Gate is 3 CPPs in width with a SDB and 4 CPPs in width with a DDB. On the other hand, a scanned flip flop (SFF) cell might be something like 19 CPPs wide with a SDB and 20 CPPs wide with a DDB (this can vary with SFF designs). As you can see the effect on SDB versus DDB has more affect on a NAND Cell size than on a SFF cell.

Cell Options
When discussing process density, I always compare the minimum cell size, but processes offer multiple options. For example, TSMC’s 7nm 7FF process offers a minimum cell that is a 6-track cell with 2 fins per transistor and a 9-track cell with 3 fins per transistor. The 9-trcak cell offers 1.5x the drive current as the 6-track cell but is also 1.5x the size. This illustrates one of the problems when comparing two product designs to each other as a way of characterizing transistor density, a high performance design would have more 9-track cells and therefore lower transistor density than a design targeted at minimum size or lower power with 6-track cells on the same process. Even the preponderance of NAND cells versus SFF cells would affect the transistor density.

Figure 1 summarize the density difference between 6-track and 9-track cells on the TSMC 7FF process. Please note the MTx/mm² parameter is the million transistor per millimeter squared based on 60% NAND cells and 40% SFF cells.

Figure 1. TSMC 7FF Density Analysis

An interesting observation from figure 1 is that a minimum area SFF cell has over 2x the transistor density of a high-performance NAND cell on the same process. There are also many other types of standard cells with varying transistor densities.

Memory Array
Most system on a chip (SOC) circuits contain significant SRAM memory arrays, in fact it is not unusual for over half the die area to be SRAM array.

The 7FF process offer a high density 6-transistor (6T) SRAM cell that is 0.0270 microns squared in area and that works out it 222 MTx/mm². In theory a lot of memory array area on a design could result in higher transistor density, however, as with a lot of things related to comparing process density it isn’t that simple.

While doing a project for a customer I analyzed 3 TSMC SRAM test chips and embed SRAM arrays in 4 Intel chips and 1 AMD chips. The SRAM arrays were on average 2.93x the size you would expect based on the SRAM cell size for the process and the bit capacity of the array. This is presumably due to interconnect and circuitry to access the memory. If we base transistor density for SRAM on the SRAM cells in the array the density drops to 75.84 MTx/mm² although there are certainly some transistor in the access circuitry that this isn’t counting.

Other Circuits
Certain SOC designs may also include analog, I/O and other elements that have significantly lower transistor density than minimum cells.

Conclusion
The bottom line to all this is that if you could implement the same design, say an ARM core with the same amount of SRAM into different processes you could use actual designs to compare process density, but since that isn’t available then some type of representative metric that can be consistently applied is needed. When I compare processes, I compare transistor density for a minimum size logic cell with a 60% NAND cell/40% SFF cell ratio. This is not a perfect metric but compares processes under the same condition. I also want to mention that for processes that are in production my calculations are based on dimensions measured on the product, typically by TechInsights and are not based on information from the individual companies I am covering. I do use information from the company announcements when estimating future process density.

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Can TSMC Maintain Their Process Technology Lead

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May 26, 2020April 14, 2022

Design in the Time of COVID

Design in the Time of COVID
by Bernard Murphy on 05-26-2020 at 6:00 am
Categories: Arteris, IP
1 Comment

There’s a lot of debate about how and when we are going to emerge from the worldwide economic downturn triggered by the pandemic. Everyone agrees we will emerge. This isn’t humanity’s first pandemic, nor will it be our last. But do we come out quickly or slowly? And what does the economy look like on the other side, particularly for the domain we care about – electronic design?

The balance of opinion I have seen comes out on the side of a slow recovery. We’re still at least 18 months away from a vaccine that might allow a return to the heady pre-COVID days. Before we get there, early indications are that no matter how eager politicians may be to restart the economy, consumers are going to be a lot more cautious. If we have more repeats of hotspots and lockdowns, that caution is going to become more embedded in our psyches. Worse yet, many of us are going to have a lot less discretionary income. It’s going to take time to get the people who lost jobs back into the workforce and making at least what they were making in 2019.

This has to have some effect on chip and system design. In some areas a positive effect – anything supporting remote work will benefit, particularly datacenters (just look at Intel’s recent performance). Advances in transportation are less clear. I’d guess for at least a year, maybe more, travel restrictions will still be fairly vigorous and we’ll be much more eager to safely distance than have in-person meetings. Companies will like this, too – lower marketing and sales support overhead. Full autonomy in cars was already looking like a long-term bet; I can’t see these changes speeding up that transition. Smartphones, our portable computers, will still do well as will wireless infrastructure (supporting all this increased traffic). Health wearables, if they actually work, could be promising.

Other stuff – cameras, GoPros, scooters, drones, etc., etc. – not so much. Thank our restricted range, also our restricted bank accounts. There’ll still be some applications, e.g. drones for policing, but consumer volume will drop. Even city, county, state and federal spending will drop. We have to pay off that $2T+ somehow, and that with reduced tax revenues. We consumers will pay for what we absolutely must have – remote connectivity, but not clear we’ll have a lot left over after we’ve paid for that. Some design-start volume has to shrink here, quite likely shifting to new health-centric and other COVID-triggered applications.

Now this is just my view. I could be wrong in details, very likely I am. But it’s difficult to believe that while the rest of the economy collapses around us, everything will still be just peachy in chip design and we can carry on doing everything the way we always have. It seems more likely we’ll have to adapt, quite possibly quickly. No problem, we’re used to that.

In the process we’re going to have to re-examine what are our core strengths and what are our weaknesses. We need staffing in new areas (AI, health, …) and that has to come from existing staffing. Is there some part of the operation adding $2-3M in cost per year and limiting new product introductions because that function can handle only 1-2 designs per year? Is there another way we could do that which might cost less and would allow us to spin 5-10 designs per year?

Kurt Shuler (VP Marketing at Arteris IP) has an answer. He tells me there are still a number of good-sized product companies building and maintaining their own on-chip interconnect IP. Not because those fabrics are provably better NoCs – evals against Arteris tend to prove otherwise – but because the need to control the NoC in-house has become axiomatic, not permitting challenge.

The best way to approach such cases unemotionally is through an ROI analysis, comparing costs, turn-times and risk for the in-house approach versus a 3^rd party solution. Arteris IP developed a spreadsheet analysis which will do those calculations for you. You can plug in your own numbers: Volumes, price per chip, cost per chip, time taken in each phase of development, area overhead, etc. This spreadsheet was developed with a major semiconductor company facing similar problems. Well-grounded in their view of reality, not an IP marketing view.

You might want to check this out. You can download the spreadsheet from HERE.

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May 25, 2020January 27, 2022

CEO Interview: Robert Blake of Achronix

CEO Interview: Robert Blake of Achronix
by Daniel Nenni on 05-25-2020 at 10:00 am
Categories: Achronix, CEO Interviews, eFPGA

Achronix came to SemiWiki in 2017 and we added a chapter on the history of Achronix in our update version of “Fabless: The Transformation of the Semiconductor Industry”. So yes we know quite a bit about Achronix and the FPGA business so it was a pleasure to do a CEO Q&A with Robert Blake. First lets take a look at his biography:

“Robert Blake has worked in the semiconductor industry for over 25 years. Prior to Achronix Semiconductor he was the Chief Executive Officer of Octasic Semiconductor based in Montreal, Canada. Mr. Blake worked at Altera in a variety of sales, marketing and general management roles. As Vice President of Product Planning he was responsible for defining Altera’s programmable logic product solutions. He has been developing ASIC and programmable logic for high speed telecom and network applications for over 17 years. Prior to Altera, he worked at LSI Logic and Fairchild where he developed ASIC technology. He holds a MEng. in Business and Microelectronics and BSc. in Applied Physics & Electronics from the University of Durham in England.”

How is Achronix’s managing through the current business climate? Are you seeing any changes in demand for Achronix FPGA and eFPGA IP?
Achronix continues to accelerate the development of both our 7nm Speedster7t FPGA product family and our Speedcore eFPGA IP. Even with the expected slow down in the global economy this year we will have a record year for sales with strong demand for all of our new products including Speedster 7t FPGAs, Speedcore eFPGA IP and our new VectorPath accelerator cards. We are seeing new design activity for our products in all geographies and target markets including compute acceleration, communications infrastructure, 5G wireless, test and measurement and most recently automotive. I am proud of the seamless transition that our worldwide employees have made to working from home. We have provided all of our employees the resources, connectivity and home office equipment necessary to ensure they can maintain their productivity. We are continuing to hire broadly in sales, design and software engineering, application and marketing. Overall this is the time for Achronix to push firmly on the accelerator peddle to ensure we will exit this global pandemic with a strong product portfolio and expanded global workforce to support new design activity with our products.

What customer requirements will drive further innovation in the FPGA industry?
Customers ask for our help to innovate their products. Our technology can be applied to solve a broad range of data acceleration challenges. At a high level, they need more system performance, but they must deliver this performance at a lower cost and reduced power consumption. Our products blend ASIC level performance and power efficiency with the flexibility inherent in FPGAs, that enables them to quickly adapt to changing workloads and algorithms. These requirements, especially the need to adapt to ever changing data processing requirements, will drive continued innovation in the FPGA industry.

What is Achronix’s strategy to differentiate and compete with Intel and Xilinx?
Unlike some of our competitors, we recognized very early that there are three critical components required to build the best FPGA for data acceleration applications. First, we needed to develop the most flexible logic, embedded memory and advanced compute engines. Next, we needed very high bandwidth external memories (GDDR6) and seamless connectivity to the highest performance PCIe and Ethernet interfaces – Speedster7t includes multiple ports of PCIe Gen 5 and 400G Ethernet. The third, and probably most critical component of our Speedster7t FPGA family, is the addition of a very high performance, low latency 2D NoC. High speed compute and networking applications require computation on vast amounts of data and the Speedster7t 2D NoC is the highest bandwidth and most efficient way to move this data between the communications ports, external memories and the core compute or data processing fabric. The data in these applications is like the fuel flow to a high performance engine. If you starve the engine of fuel you lose performance. We have solved all these problems in our new Speedster7t FPGA family.

Why did Achronix start offering eFPGA IP in addition to standalone FPGA devices?
The strategy to offer eFPGA IP was obvious if you simply look at the trends in the semiconductor industry for the last 50 years. Companies integrate more functionality. They look at components that are on their printed circuit boards and ask three simple questions: are adjacent product compatible from a silicon process standpoint; will they add value if integrated; and will they improve performance, reduce power consumption and reduce board area? Back in the 80’s, most companies used standalone CPUs from Motorola or National Semiconductor. Then ARM came along and offered a large range of CPU cores for integration. Achronix has quickly established ourselves as the leader in delivering high performance eFPGA IP cores. Our customers have integrated custom sized eFPGA IP with exactly the resource mix of logic and memories and compute engines that their application requires. They are already being used in high volume applications with greater than 10M eFPGA IP cores shipped per year.

The primary reason to integrate embedded FPGA fabric is higher performance. Integration eliminates performance and latency bottlenecks between an ASIC and a standalone FPGA, but there are other significant advantages as well including up to 90% reduction in BOM cost and less than 1/2 the power consumption when compared to standalone FPGA solution. Achronix is the only company to offer both high performance standalone FPGA devices and a cost migration path to integrate that same technology into a customer ASIC. We believe this will be a growing trend where unique data acceleration challenges cannot be adequately solved by off-the-shelf FPGA solutions and where Speedcore eFPGA IP is a perfect fit.

What applications are you targeting for your new 7nm Speedster7t FPGA?
Speedster7t FPGAs address a growing need for data acceleration challenges in applications such as networking, data center, test and measurement, compute acceleration, AI/ML, 5G and military applications.

How do you think Achronix’s business will do over the next 3 to 5 years?
Achronix financials are strong and our innovative technology portfolio will enable us to enjoy significant growth over the next 3-5 years. We have tremendous interest from an expanding customer base that will use our latest generation products to deliver new levels of performance innovations in their products. We continue to invest in both our hardware and EDA software tools together with our partners to accelerate the design phase and adoption of our technology. During this challenging time we will continue to innovate and find new ways to effectively deliver our technology into customer’s systems. We are exited about our future.

About Achronix Semiconductor Corporation
Achronix Semiconductor Corporation is a privately held, fabless semiconductor corporation based in Santa Clara, California and offers high-performance FPGA and embedded FPGA (eFPGA) solutions. Achronix’s history is one of pushing the boundaries in the high-performance FPGA market. Achronix offerings include programmable FPGA fabrics, discrete high-performance and high-density FPGAs with hardwired system-level blocks, datacenter and HPC hardware accelerator boards, and best-in-class EDA software supporting all Achronix products. The company has sales offices and representatives in the United States, Europe, and China, and has a research and design office in Bangalore, India..

Follow Achronix
Website: www.achronix.com
The Achronix Blog: /blogs/
Twitter: @AchronixInc
LinkedIn: https://www.linkedin.com/company/57668/
Facebook: https://www.facebook.com/achronix/

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May 25, 2020August 25, 2020

China’s Position in the Global Semiconductor Value Chain

China’s Position in the Global Semiconductor Value Chain
by Bart van Hezewijk on 05-25-2020 at 6:00 am
Categories: China
8 Comments

In this third article about China’s role in the global semiconductor industry I analyse the current state of affairs of the Chinese semiconductor industry in different segments. In the previous articles, I looked at the possible effects of a US-China decoupling in the semiconductor industry and the impact of the Big Fund and Chinese investments in semiconductor R&D. Both articles are available in Chinese as well: decoupling, Big Fund (文章翻译成中文: 脱钩, 大基金). In my next article that will be published soon, I will give an updated analysis of the impact of the US-China tech war on the semiconductor industry.

China aims to accelerate the development of the domestic semiconductor industry and reduce the reliance on imports of chips. But the semiconductor industry’s global value chain spans a wide variety of segments such as equipment, materials, software, design, manufacturing, assembly and testing.

One of the conclusions of my previous article was that Chinese (government) investments are often focused on increasing manufacturing capacity and acquiring existing technology instead of real new technology development. Besides having fabs to actually make chips, the tools and equipment needed for chip manufacturing and testing, the software needed to design chips, and the design capabilities themselves are all important in the semiconductor value chain.

In this article I look at the position of (mainland) China, the United States (US), and the rest of the world (ROW) in five different segments of the semiconductor value chain: equipment (EQP), Electronic Design Automation software & Intellectual Property core (EDA & IP), design/fabless & Integrated Device Manufacturer (DES & IDM), foundry (FOU), and Outsourced Semiconductor Assembly & Test (OSAT).

Table 1 shows the combined revenues of the major companies in these five segments for each of the three regions. I included the sales data of 136 companies: 27 equipment (6 from China, 13 from the rest of the world, and 8 from the United States), 9 EDA and IP (1 CN, 4 ROW, 4 US), 76 design and IDM (30 CN, 23 ROW, 23 US), 12 foundry (4 CN, 7 ROW, 1 US), and 12 OSAT (5 CN, 6 ROW, 1 US). Sales data is available from the annual report for listed companies, but unfortunately there are quite some relevant semiconductor companies that are not listed (e.g., Arm, GlobalFoundries, HiSilicon, Kioxia, Mentor Graphics, UNISOC). For 15 of those I based the sales data on publicly available information. For another 65 companies no sales information was available so they are not included in the analysis, which means the consolidated numbers in this article are a lower limit of the actual numbers. I would like to emphasise that the list of companies mentioned in this article is by no means exhaustive, but I believe it provides a representative overview of the global semiconductor value chain (with the materials segment excluded). As the objective of this article is to provide an overview of the Chinese semiconductor industry, I included more (and smaller) companies from China. For the rest of the world and the United States I included only the largest and most important companies. (i)

Table 1: Semiconductor sales by segment and region.

If we look at all sales data across five segments the whole semiconductor industry combined sales is US$ 571.8 billion. US headquartered companies account for 47%, companies from the rest of the world for 45%, and China based companies for 7%. For all three regions, design & IDM is the segment with highest sales. Globally, design & IDM accounts for 71% of all sales, followed by equipment (13%) and foundry (10%). OSAT (5%) and EDA and IP (2%) generate considerably less revenue.

China is relatively strong in OSAT, mainly because of JCET which accounts for 57% of China’s revenue in this segment. For EDA & IP and especially equipment, China is far behind the United States and rest of the world. The rest of the world region’s strongest segment is foundry, because of TSMC (78% of the region’s foundry revenue) and UMC (11%) from Taiwan. In addition, the rest of the world region is leading in OSAT, again because of Taiwanese companies such as ASE (73% of the region’s OSAT revenue) and PowerTech (12%). The US’ main strengths are in design & IDM and EDA & IP. Intel is the world’s largest semiconductor company based on revenue (US$ 72 billion) and Micron, Qualcomm and Broadcom all have more than US$ 20 billion sales. For EDA software all three global leaders are US headquartered: Synopsys, Cadence Design Systems, and Mentor Graphics (owned by German Siemens). Equipment is a narrow victory by the rest of the world region, led by Dutch ASML (#2 equipment company globally) and Japanese Tokyo Electron (#3), over the US, with Applied Materials (#1), Lam Research (#4), and KLA (#5).

Figure 1 also represents the sales data and includes all companies that account for at least 10% of sales of their segment in their own region.

Figure 1: Semiconductor sales by segment and region.

Further breaking down the revenues for rest of the world gives the following ranking (sales above US$ 10 billion):

United States, US$ 270.9 billion
Korea, US$ 80.9 billion
Taiwan, US$ 75.9 billion
Japan, US$ 50.0 billion
China, US$ 41.3 billion
The Netherlands, US$ 25.4 billion

Korea is home to two of the largest IDMs, Samsung (#2, US$ 56 billion sales) and SK Hynix (#3, US$ 23 billion). In addition to the foundry and OSAT companies mentioned above, Taiwan is also home to design companies such as MediaTek, Novatek and Realtek. Japan’s strength is in equipment with Tokyo Electron, Dainippon Screen and Advantest, and IDM with Kioxia, Sony Semiconductors Solutions, and Renesas, amongst others. China’s largest semiconductor companies are design companies Unis and HiSilicon, foundry SMIC and packaging and test provider JCET. More than half of the Netherlands’ semiconductor revenue is generated by lithography equipment supplier ASML but ASM International (equipment, US$ 1.4 billion), NXP (IDM, US$ 8.9 billion) and Nexperia (IDM, US$ 1.4 billion) also contribute generously.

In the remainder of this article I will look at the five segments separately, with special attention for the performance of Chinese companies compared to the global leaders.

Equipment

Many different types of tools and equipment are needed to make chips. Important steps in the IC manufacturing process include lithography, ion implantation, deposition (e.g., CVD, PVD), etching, cleaning, and testing. The major equipment suppliers are from the US, Japan and the Netherlands, but China is also trying to develop its domestic semiconductor equipment industry.

The lithography equipment segment is dominated by Dutch ASML with a market share of 85% and the only relevant competitors are Canon and Nikon from Japan. China’s sole lithography equipment maker is Shanghai Micro Electronics Equipment (SMEE) and its most advanced tool at present enables 90nm chip production. ASML sold their first lithography systems that could produce complex 90nm chips in 2004 already (16 years ago!).

For the deposition equipment segment there are more competitors. Some of the big players are active in PVD and CVD such as Applied Materials (US), Tokyo Electron (JP) and Lam Research (JP), but also smaller companies such as Aixtron (DE), ASM International (NL), Evatec (CH) and Ulvac (JP). NAURA, resulting from the 2017 merger between Sevenstar Electronics (established in 2001) and Beijing North Microelectronics (NMC, also 2001), is the largest semiconductor equipment company in China and active in this field.

Another more established Chinese equipment company is Advanced Micro-fabrication Equipment (AMEC). The Shanghai-based company that produces etch equipment and MOCVD tools was founded in 2004 and was in the first batch of companies to get listed on the new Shanghai Stock Exchange Science & Technology Innovation Board (or STAR Market) in 2019. Qualcomm participated in AMEC’s B round in 2007 and is still one of its shareholders. AMEC’s etch equipment is verified by TSMC for its 7nm process.

Other companies active in cleaning, packaging and testing equipment include Advantest (JP), ASM Pacific Technology (SG), Dainippon Screen (JP), and Teradyne (US). More Chinese semiconductor equipment companies worth mentioning are Hangzhou Changchuan Technology, Kingsemi, and PNC Process Systems but their revenues are well below US$ 150 million.

Table 2: Semiconductor equipment companies’ sales and R&D spending per region.

EDA & IP

Electronic Design Automation software and IP core is another area where China still lags far behind. The vast majority of the Chinese EDA market is taken by the three global leaders Synopsys, Cadence, and Mentor. There are some Chinese companies active in the EDA segment though, such as Cellix, Empyrean, ProPlus, Semitronix, and Xpeedic. Empyrean seems to lead the Chinese domestic field, but I could not find financial information for any of these companies. Cellix is reported to be preparing for a listing on the STAR market and ProPlus closed an investment round in April 2020 in which Intel reported it participated.

Table 3: EDA software & IP core companies’ sales and R&D spending per region.

An IP core is intellectual property of a licensing party that can be used as a building block for chip design. IC design companies use third party IP and their own IP to design their chips. The leading company in this field is UK-based but Japanese (Softbank) owned Arm Holdings. Basically, all smartphones and most IoT devices use Arm’s processor architecture. Softbank closed the Arm acquisition in September 2016, and just 1.5 years later, in April 2018, Arm China (also known as Arm mini China) was created. Arm China is 51% controlled by a consortium of Chinese investors and Arm owns 49%. Arm China sells and licenses Arm (UK) technology in China but has also gradually moved to developing its own (Chinese) IP. For example, Arm China has developed a design that allows Chinese-made chips to run a cryptographic algorithm built by China’s State Cryptography Administration.

Imagination Technologies is also UK-headquartered but was acquired by Cayman-based and Chinese funded private equity fund Canyon Bridge in November 2017. In April 2020 Imagination announced plans to appoint new board directors from China Reform Holdings, the major investor in Canyon Bridge. After the UK government expressed concerns this proposal was withdrawn. Imagination mainly develops IP for Graphic Processor Units (GPUs). Apple used to be Imagination’s biggest customer until 2016 and earlier this year they signed a new multi-year license agreement under which Apple will have access to a wider range of Imagination’s IP.

Previously mentioned Synopsys and Cadence are also active in the IP core licensing field, and so is US-based Rambus, mainly licensing memory technology. In China, VeriSilicon is the leading (but loss making) company in this field. Established in 2001, it’s investors include Intel, Samsung, Xiaomi, the Big Fund, and Walden International. VeriSilicon has announced the intention to list on Shanghai’s STAR market.

Besides the Arm architecture, there are only a few other processor architectures. Like Arm, MIPS and RISC-V are so called RISC (Reduced Instruction-Set Computer) architectures and x86 is a CISC (Complex Instruction-Set Computer) architecture. In general, CISC is more suitable for high performance processors (complexity and speed; e.g., servers) and RISC for power efficiency (e.g., smartphones).

MIPS Technologies developed the MIPS architecture in the 1980s and licensed it to chip designers. Imagination Technologies bought MIPS Technologies in 2013 and sold it to US based Wave Computing prior to the Canyon Bridge acquisition of Imagination in 2017. Wave Computing filed for bankruptcy in April 2020 but there are reports that MIPS will continue its business independently. MIPS is not nearly as successful as Arm but in China it is used by Loongson (formerly known as Godson and creator of China’s first domestic CPU) and Ingenic (designing CPUs and IoT and wearables chips).

RISC-V is an open source project that started at UC Berkeley in the US in 2010 and aims to provide royalty free instruction set architectures. RISC-V started in academia but in 2015 the RISC-V Foundation was established to create a community for standardisation and improvement through open collaboration. In March 2020 the RISC-V International Association (RVI) was incorporated in Switzerland after reflecting on the geo-political landscape and to calm “concerns of political disruption to the open collaboration model”. RVI mentions explicitly on its website that “there have not been any export restrictions on RISC-V in the US and we have complied with all US laws. The move does not circumvent any existing restrictions, but rather alleviates uncertainty going forward.” RVI has never received or pursued funding from any government and currently has more than 500 members, including Alibaba, Huawei, the Institute of Computing Technology of the Chinese Academy of Sciences, and VeriSilicon from China. US members include Western Digital, Nvidia, and Rambus. RISC-V is relatively new so no major competition for Arm yet, but the community is moving fast and in the current geopolitical climate open source, which is not export-controlled by definition, may be the way forward for Chinese chip design companies.

Design & IDM

For this article I combined the fabless design companies and Integrated Device Manufacturers in one segment as they all have the capabilities to design chips. The fabless design companies rely on foundries to manufacture the chips they designed, while IDMs make their chips in-house. Design & IDM is the largest segment of the semiconductor value chain across regions (72% of total semiconductor sales for China, 61% for rest of the world, and 81% for US); it also has the most companies included in this analysis for each region. The world’s biggest semiconductor companies are all active in this segment: IDMs Intel, Samsung, SK Hynix, and Micron, and fabless design companies Qualcomm and Broadcom. They all have more than US$ 20 billion sales; only foundry TSMC belongs to the same category with US$ 34.6 billion sales. Within the Design & IDM segment, the US is the clear leader with 54% of its sales, followed by the rest of the world with 39% and China’s 7%.

Table 4: IC design companies’ and IDMs’ sales and R&D spending per region.

The biggest Chinese chip design companies are Unis (also known as Unisplendour) an HiSilicon (fully owned by Huawei). HiSilicon develops SoCs (System on a Chip; multiple components such as CPU, GPU, and memory on one chip) based on Arm architecture. HiSilicon designs smartphone chips (Kirin), server chips (Kunpeng), and smartphone modems (Balong). The newest Kirin 810 outperformed competitor Qualcomm’s Snapdragon 855 SoC in the AI Benchmark test. Qualcomm is the global market leader in smartphone SoCs and has held the same position for the China market for a long time. Until Q1 2020 when HiSilicon led the China smartphone SoC shipments ranking for the first time. COVID-19 has a big impact though, as smartphone SoC shipments decreased more than 44% compared to Q1 2019.

Unis is part of the Tsinghua Unigroup ecosystem. Unigroup’s subsidiaries include fabless companies Pango Microsystems, Tongxin Microelectronics, Unic Memory, Unigroup Guoxin, UNISOC (formerly known as Spreadtrum), and Unis; foundries UniIC Semiconductors, XMC and YMTC; and OSAT company Unimos. Unis and Guoxin are listed companies. UNISOC primarily designs entry-level smartphone and feature phone chips, which are very popular in India and Africa.

Another Chinese State-Owned Enterprise (SOE) that is very active in the semiconductor industry is China Electronics Corporation (CEC). CEC’s companies include fabless Anlogic, CE Huada Tech, Huada Semiconductor, Microne, Phytium Technology, Shanghai Belling, Solantro (a Canadian company acquired in 2018 and now known as Huada Semiconductor North American R&D Centre), and Solomon Systech; foundry GTA Semiconductor; and OSAT company Chipadavanced. CE Huada Tech, Shanghai Belling, and Solomon Systech are listed companies.

Chinese consumer electronics company (and smartphone vendor) Xiaomi has been active in chip design with its subsidiary Pinecone established in 2014. Early 2017 Pinecone revealed the Surge S1 chipset, but Xiaomi’s 5C smartphone which used the S1 failed because of high power consumption and heat output. In April 2019 Xiaomi announced it would spin off and take a 25% stake in a new company Big Fish Semiconductors to focus on the development of AI and IoT chips. Pinecone (51% owned by Xiaomi and 49% by China’s Datang Telecom) will keep developing smartphone chips. Xiaomi also invested in IP provider VeriSilicon and is its second biggest shareholder behind the Big Fund.

The Chinese design companies mentioned above mainly use Arm architecture but some Chinese companies work with x86 architecture. Because x86 is a CISC architecture, it is the dominant architecture in the server market. Recently though, Arm and RISC-V based processors seem to get some more traction. Intel is market leader in the x86 processor market but AMD (also from the US) has been gaining market share over the last years thanks to its Ryzen chip architecture. Besides them, only VIA Technologies from Taiwan has a x86 CPU license but VIA has not been successful at making the products to get closer to Intel and AMD’s market share.

Interestingly though, on May 8 the first Chinese PCs with domestically developed x86 CPUs were released. They use the KX6000 processor series made by Zhaoxin, a joint venture between VIA Technologies and the Shanghai local government established in 2013. The performance of these KX6000 processors, which are based on architecture developed by VIA’s US subsidiary Centaur Technology, is still far behind Intel and AMD’s current offerings, but it’s definitely suitable for its intended government use. This is an important step in China’s plans to reduce dependence on foreign technology and Zhaoxin has ambitious plans to bridge the gap with Intel and AMD.

AMD also set up a joint venture in China, with partners including high performance computing maker Sugon and the Chinese Academy of Sciences. Tianjin Haiguang Advanced Technology Investment Co (THATIC or Higon), set up in 2016, actually comprises two JVs with AMD holding 51% shares of Chengdu Haiguang Microelectronics Technology (also known as HMC) and 30% of Chengdu Haiguang IC (also known as Hygon). AMD exported IP to subsidiary HMC and Hygon would customise the designs before they were sent to GlobalFoundries in the US for manufacturing. This allowed the Chinese side to call the processors ‘Chinese’ and AMD to comply with all relevant export control legislation. Until June 2019 that is, because then the US government added AMD’s JVs to the Entity List because Sugon had acknowledged military end uses and end users of its high-performance computers. The consequence is that US companies need to apply for a license before exporting products and technology to these entities and the US government follows a ‘presumption of denial’ policy.

Intel set up a collaboration with Tsinghua University and Montage Technology in 2016. Based on Intel’s x86 Xeon architecture and Tsinghua developed technology, Montage designed the Jintide CPU. Montage Technologies is listed on Shanghai’s STAR market since July 2019 and Intel owns 9% of its shares.

One Sino-American collaboration in the semiconductor industry that did not last long is the joint venture Qualcomm set up in 2016 with the Guizhou provincial government. The JV, Huaxintong Semiconductor Technologies (HXT), 55% owned by Guizhou province and 45% owned by Qualcomm, focused on designing server chips based on Arm architecture. In November 2018 HXT announced that the StarDragon 4800 had started mass production. This processor is similar to Qualcomm’s Centriq 2400 series with a modified crypto module to meet China’s commercial cryptographic algorithms standards. In April 2019 it was reported that the joint venture would shut down.

RISC-V architecture is another area where Chinese companies have become increasingly active. Alibaba Group acquired Hangzhou C-Sky Microsystems in 2018 and reorganised its chip R&D activities into Pingtouge Semiconductor (also known as T-Head). In July 2019 Pingtouge announced it developed a 16-core Xuan Tie 910 RISC-V CPU (XT910) and claimed it was the most powerful design based on RISC-V IP yet. Two months later Alibaba also announced the Hanguang 800 AI inference chip made with TSMC’s 12nm process. The Neural Processing Unit (NPU) is capable of handling complex tasks such as product search, image analysis, and personalised recommendations on Alibaba’s e-commerce platforms.

Foundry

The semiconductor pure play foundry segment is dominated by the rest of the world region, mainly because of Taiwan’s TSMC, the world leader in this field by far. The number two (UMC) and three (Vanguard) foundries from the rest of the world region are also based in Taiwan. The only US-based foundry is Abu-Dhabi owned GlobalFoundries and in China the largest foundries are SMIC and Huahong Grace. For some other Chinese foundries such as Huali (also from Huahong Group), YMTC and XMC (both part of Tsinghua Unigroup), and CXMT, I have not found financial data.

Table 5: Foundry sales and R&D spending per region.

SMIC has made quite some progress over the years and is now capable of 14nm mass production, although the defect rates are still very high according to some sources. Industry leader TSMC and IDM Samsung are already mass producing 7nm (and TSMC starting 5nm), while GlobalFoundries announced it stopped 7nm development because of the high costs involved. On May 11 it was announced that SMIC had started mass production of Huawei/HiSilicon’s Kirin 710A on its FinFET 14nm process. Although these chips are not current state-of-the-art (Kirin 710 was launched in July 2018), this is a significant development for China’s semiconductor industry as it is the first time that Huawei uses a foundry other than TSMC to make its smartphone chips.

Other Chinese foundries, focused on developing memory chips, are YMTC and CXMT. The memory market is dominated by Samsung and SK Hynix from Korea and US-based Micron. On April 13, YMTC announced it has developed 128-layer 3D NAND flash memory chip X2-6070, based on its own Xtacking architecture. Whether X2-6070 will indeed be a success depends on multiple factors, including the timing of mass production (probably H1 2021) and yield (the proportion of chips on a wafer that work properly). So after designing the memory chip, getting the production process right will be the next big challenge for YMTC.

CXMT, China’s new DRAM memory maker (established in 2016, then known as Innotron), announced at the end of April that they signed a long-term patent license agreement with US-based Rambus to get access to a wide variety of DRAM patents. This deal will strengthen and diversify CXMT’s IP portfolio. Through previously signed licensing agreements, CXMT already has access to Qimonda’s IP (Qimonda spun off from Infineon in 2006 and was the world’s second largest DRAM company at the time but ceased operations in 2011).

OSAT

Half of the top 10 global Outsourced Semiconductor Assembly and Test (OSAT) companies are from Taiwan. Market leader ASE Group’s market share is 47%, followed by Amkor from the US and JCET from China. With the other 4 Taiwanese companies, two Chinese companies (TFME and Tianshui Huatian) and one Singaporean company complete the top 10.

Table 6: OSAT companies’ sales and R&D spending per region.

This analysis shows that China is still a relatively small player in the global semiconductor value chain, except for the OSAT segment where China holds more than 20% of the global market. There are 3 Chinese companies in the global top 6 OSAT companies, while 6 years ago only JCET made the top 10. This also shows that the developments in the Chinese semiconductor industry can go fast.

However, in other segments, particularly semiconductor equipment and EDA & IP, China is still far behind. Although AMEC has developed tools which are used in many foundries, AMEC is still a small player (around #20) among all the semiconductor equipment makers ranked by revenue. And size matters. To stay competitive in the semiconductor industry, companies need to invest in R&D and with higher sales companies can invest more in new technological developments and innovation.

Table 7: Average R&D investment as percentage of sales across segments and regions.

There are no huge differences between the three regions when it comes to companies’ average R&D spending as percentage of sales. American design & IDM companies spend more on R&D than their competitors from China and the rest of the world, and Chinese foundry and OSAT companies on average spend a larger part of their revenue on R&D than others. For the foundry segment, this is mostly attributable to SMIC’s R&D spending (22.1%) which is much higher than any other foundry in the world (Chinese Silan ranks second with 10.7% and TSMC is third with 8.5%). Looking at the actual R&D expenditures (in dollars), China’s share of global R&D expenditures is indeed higher than its share of global sales for the foundry (18% vs 8%) and OSAT (23% vs 21%) segments. However, for both these segments the rest of the world’s R&D expenditures are much higher than those of China; for foundry the rest of the world region spends 4.6 times as much on R&D as China, and for OSAT they spend 2.9 times as much.

For the equipment and EDA & IP segments there are no apparent differences between regions (and like for foundry and OSAT, the sample sizes on which these averages are based are small) but for design & IDM, US companies on average spend a higher percentage of their revenue on R&D than others. Because these are also the biggest companies in the whole industry, measured by sales, this is a major competitive advantage of the American semiconductor industry. Although US design & IDM companies account for 54% of global design & IDM sales, they are responsible for 72% (or a combined US$ 38.9 billion for the 22 companies included in this analysis) of global R&D expenditures in this segment. The amount of money Intel spends on R&D, US$ 13.4 billion, is higher than the annual revenue of all semiconductor companies in the world except 8 (Samsung, TSMC, Qualcomm, Micron, SK Hynix, Broadcom, Applied Materials, and Texas Instruments).

The absence of major differences in R&D spending as percentage of sales between regions for the equipment and EDA & IP segments does not mean that it will be easier for China to catch up in these areas. For example, ASML spends around US$ 2.2 billion on R&D, which is twice the annual revenue of all six Chinese semiconductor equipment companies included in this analysis combined. For EDA the whole industry basically depends on the three major vendors Synopsys, Cadence, and Mentor. Although quite a few Chinese companies are developing EDA tools, none of them are competitive as they are not comprehensive enough (no complete design flow) and because the most advanced fabs and foundries will not use them, it is extremely difficult for them to get a better understanding of the processes and improve their software.

Fortunately for China, some developments provide a more positive outlook for growing the domestic semiconductor industry. The establishment of Arm China, the acquisition of Imagination Technologies, Intel investing in Montage Technology and ProPlus, the IP licensing deal between Rambus and CXMT, and the whole development of the RISC-V movement, could bring opportunities to strengthen China’s semiconductor industry. In the chip design field, HiSilicon is already world class and entered the top 10 of semiconductor sales leaders for the first time in Q1 2020 according to IC Insights. Recent achievements including Zhaoxin’s first domestically developed x86 CPU, Pingtouge’s RISC-V based CPU and AI inference chip, and YMTC’s 3D NAND flash memory chip, indicate progress is certainly being made in Chinese chip design. The recent announcement that SMIC is mass producing HiSilicon’s Kirin 710A on 14nm FinFET is a significant development for China’s chip manufacturing.

But… the challenges for particularly the equipment and EDA segments remain, and it is extremely difficult to catch up with industry leaders (also in design and manufacturing) when they spend much more on R&D and thus maintain their technology leadership. The establishment of the Big Fund is one (small) step to help Chinese semiconductor companies to overcome this gap, and recently there seems to be a trend for more Chinese semiconductor companies to go public, for example on Shanghai’s STAR market. AMEC and Montage Technology are already listed there, SMIC, VeriSilicon and Cellix announced plans to do so, and Imagination Technologies, UNISOC, and Horizon Robotics are also rumoured to file for an IPO. Although companies understandably look for more funding and resources, they should also keep in mind that the interests of investors (quick returns) do not always align with those of the companies themselves (long term commitment to R&D). There are no quick wins for companies that still need to establish their position in the global semiconductor value chain.

And then of course the biggest stumbling block for the development of China’s domestic semiconductor industry is the current geopolitical climate and recent actions taken by the US government that restrict American, and since May 15, 2020 also non-American, companies from doing business with some Chinese semiconductor companies. I will write more about the impact of the US-China tech war on the semiconductor industry in my next article. So stay tuned!

I would like to end this article with a suggestion for further reading that really gave me a better understanding of the history and development of the Chinese semiconductor industry. It is very informative and I really enjoyed reading the article originally written by Boss Dai (戴老板), published on his WeChat account on May 15, 2018: 中国芯酸往事. The article is translated into English by Jeffrey Ding and Lorand Laskai and published in the July 8, 2019 ChinaAI newsletter: The Sour Past of “China Chips”.

Bart van Hezewijk
Officer for Innovation, Technology & Science
Netherlands Innovation Network
Consulate-General of the Kingdom of the Netherlands in Shanghai
@bartvanhezewijk

(i) Note on data collection

For this analysis of the global semiconductor value chain I identified 201 companies: 100 from China, 59 from rest of the world, and 42 from the US. 121 of these companies are listed so I could get their sales and R&D spending data from their annual reports. The annual report used is the report for the fiscal year ending 31 December 2019 or earlier that year, except for Aixtron, Goodix, JCET, PowerChip, Tower Semiconductor (31 Dec ‘18), Ambarella (31 Jan ‘20), and Marvell (1 Feb ‘20).

For another 15 companies I used other publicly available data:

Arm (Softbank Group Annual Report 2019), Cambricon, GlobalFoundries, Imagination Technologies, Kioxia, Nexperia, Vanguard International Semiconductor (VIS Consolidated Financial Statements), and VeriSilicon.
For GalaxyCore, HiSilicon, Huada Semiconductor, Integrated Silicon Solutions Inc, Sanechips Technology, and UNISOC: Trendforce (2018 revenue).
For Mentor Graphics I calculated the 2019 revenue relative to Synopsys’ and Cadence’ 2019 revenue, based on their share of their combined revenues (Synopsys 46%, Cadence 33% and Mentor 21%) in 2016 and 2017 (latest available annual reports of Mentor).

For some companies their semiconductor business is a part of their total business. For these companies I only included the semiconductor revenue:

Fujitsu Semiconductor: LSI Devices within Device Solutions, 5.3% of Fujitsu Group total revenue.
Hitachi Hitech: Electronic Device Systems, 20.1% of total revenue.
IBM: Systems (includes Servers & Storage Systems), 9.9% of total revenue.
Jusun Engineering: Semiconductor (Display and Solar Cell not included), 52% of total revenue.
Mitsubishi Electric: Electronic Devices, 4.4% of total revenue.
Samsung: Semiconductor within Device Solutions (inter-company revenue not included), 28% of Samsung Electronics total revenue.
Tianjin Zhonguan: Semiconductor Device (Semiconductor Materials and New Energy not included), 0.83% of total revenue.
Wonik IPS: Semiconductor (Display and Solar not included), 55% of total revenue.

Some large companies that are active in the global semiconductor value chain are left out from the data analysis because they do not report financial data for their semiconductor related business or their data was not specific enough to be included in this analysis, e.g., Apple (US, DES), Baidu (CN, DES), Bosch (DE, DES), Canon (JP, EQP), and Nikon (JP, EQP).

May 24, 2020January 11, 2022

Contact Resistance: The Silent Device Scaling Barrier

Contact Resistance: The Silent Device Scaling Barrier
by Fred Chen on 05-24-2020 at 6:00 am
Categories: Lithography

Moore’s Law has been about device density, specifically transistor density, increasing every certain number of years. Although cost is the most easily grasped advantage, there are two other benefits: higher performance (speed) and reduced power. When these benefits are compromised, they can also pose a scaling limitation. Probably the most well-known scaling limiter for transistors is the short-channel effect (SCE) which has been covered for many years and updated for recent transistor developments like FinFETs. Much less well-known but still very important and persistent is contact resistance, i.e., the electrical resistance of the narrow contact to the much larger transistor. A higher contact resistance is damaging in either of two ways: (1) less current at the same operating voltage, which reduces performance, or (2) higher voltage for the same driving current, which increases power consumption.

The contact resistance (Rc) is usually characterized by the “contact resistivity” which actually has the units of resistance x area (ohms-cm^2). The actual resistance is computed from contact resistivity by dividing contact resistivity by the contact area. In Figure 1, the trend of contact resistance is plotted from three different references, published over a period of ten years.

Figure 1. Contact resistance trends, from various studies from 2008 to 2018 [1-3].

The earliest reference [1] is from 2008, published by Stanford. It was based on projections from the 2005 ITRS roadmap projection at the time. The second reference is from 2013 [2], from an interesting paper discussing the use of an interfacial layer. Half the authors listed were affiliated with Applied Materials, so the data for it on the graph is labeled as “AMAT”. The contact resistivity used here was 3.5e-8 ohm-cm^2. The third, most recent reference is from IMEC[3], which presented an atomistic simulation study. Its values are lower than previous projections. Specific assumptions for this case were: n+ doping of 3e20/cm^3, amorphous titanium silicide interface. The resulting calculated resistivity was 4e-9 ohm-cm^2. A lower doping would raise the resistance significantly (Figure 2). For 1e20/cm^3, with over 2 kOhm resistance, even 65 nm size contacts are a problem for many applications.

Figure 2. The contact resistance can be increased significantly by a reduction of doping (from 3e20/cm^3 to 1e20/cm^3 in this case) [3].

The red arrow in the graph marks where we are today at the bleeding edge. At this point, the contact resistance is already over 1.5 kOhm, and this is about 3 times what it was for the 90 nm node. Contact resistivity needs to get to below 1e-9 ohm-cm^2 to avoid becoming prohibitive at ~10 nm scale. Based on IMEC’s results [3], this may require doping over 1e21/cm^3, which is 2% concentration impact in silicon! It would not be the original pure silicon anymore!

Not surprisingly, the move from planar transistors to FinFETs simultaneously changed the way contacts are landed. They don’t land flat on the silicon surface anymore. Instead the contact lands on and wraps around the angled surfaces of epitaxially grown SiGe, which effectively increases the contact area. In a way, transistor contact scaling in 2D already hit the wall, and we are already operating in 3D.

Notation clarification: The notation “1e20” is the same as 1 x 10^20. Likewise, “3e-8” means 3 x 10^-8.

References

[1] L. Wei, J. Deng, L-W. Chang, K. Kim, C-T. Chuang, H.-S. P. Wong, “Selective Device Structure Scaling and Parasitics Engineering: A Way to Extend the Technology Roadmap,” IEEE Trans. Elec. Dev. 56, 312 (2009).

[2] S. Gupta, P. P. Manik, R. K. Mishra, A. Nainani, M. C. Abraham, S. Lodha, “Contact resistivity reduction through interfacial layer doping in metal-interfacial layer-semiconductor contacts,” J. Appl. Phys. 113, 234505 (2013).

[3] A. Dabral, G. Pourtois, K. Sankaran, W. Magnus, H. Yu, A. de Jamblinne de Meux, A. K. A. Lu, S. Clima, K. Stokbro, M. Schaekers, N. Collaert, N. Horiguchi, M. Houssa, “Study of the Intrinsic Limitations of the Contact Resistance of Metal/Semiconductor Interfaces through Atomistic Simulations,” ECS J. Solid State. Sci. and Tech. 7, N73 (2018).

The Largest Engineering Simulation Virtual Event in the World!

The Largest Engineering Simulation Virtual Event in the World!
by Daniel Nenni on 05-22-2020 at 10:00 am
Categories: Ansys, Inc., EDA, Events

ANSYS is the world leader in engineering simulation across multiple markets. One of those markets just happens to be semiconductor which is why ANSYS is on SemiWiki.com. Due to the pandemic ANSYS has transformed their popular live regional events to one broad virtual event “Simulation World”.

“Simulation World is world’s largest virtual event for research and development leaders and engineering simulation thought leaders and users across industries. Through a series of informative keynote presentations, industry and initiative breakout sessions, attendees will learn the latest innovations and best practices in simulation and its application in sectors ranging from automotive to semiconductor to health care. Interactive chat features will help attendees connect in real time with their colleagues around the world to ask questions and to network. And they can learn about the newest advances in simulation from leading company in a partner pavilion.”

There are four semiconductor tracks including four designer presentations which is something ANSYS is well known for with live events such as the Design Automation Conference. Talking about products is one thing, talking about real problems those products solve is quite another, absolutely.

Here are the customer presentations:

Nitin Navale, CAD Manager, Xilinx Session title: Elastic Compute Scalable Design Methodologies for Next-Generation FPGAs Wednesday, June 10

Dai Dai, Mixed Signal Design Manager, NVIDIA Session title: Optimizing Electromagnetic Crosstalk and Power Distribution for HighSpeed Serial Links on Silicon Wednesday, June 10

Jiaze Li, Senior Engineer, Qualcomm Session title:Novel RTL Power Regression and Minimization Workflow for Mobile GPU Cores Thursday, June 11

Erman Timurdogan, Director, Analog Photonics Session title: Designing Large-Scale Silicon Photonics Integrated Circuits through PDK Component Library Thursday, June 11

You will also want to catch John Lee’s keynote:

John Lee, Vice President and GM, Semiconductor BU Session title: Reducing Your Project Risk in a Time of Great Change Wednesday, June 10

For those of you who don’t know John he is an EDA legend in the making. John started his career Co-founding Performance Signal Integrity, a startup from Carnegie Mellon University. Avant! acquired PSI in 1994 which is where I first met John. Avant! was acquired by Synopsys in 2002. John went on to Co-found Mojave Design, which Magma acquired in 2004, Magma and was acquired by Synopsys in 2012. John then assembled a team that built the first big data platform for chip design which was acquired by ANSYS in 2015.

Bottom line: When John speaks you listen, absolutely.

And what simulation event would not include academic research:

Sung-Kyu Lim, Professor, Georgia Tech Session title: Thermal Issues and Solutions for 3D ICs: Latest Updates and Future Prospect Thursday, June 11

Makoto Nagata, Professor, Kobe University Session title: A C-P-S Simulation Technique of Power-Noise Side Channel Leakage in Cryptographic Integrated Circuits Thursday, June 11

To round things out the ANSYS staff of experts weigh in:

Ankur Gupta, Senior Director, Application Engineering Session title: Not Your Dad’s Power Integrity Analysis Wednesday, June 10

Anand Raman, Senior Director, Key Global Accounts Session title: Top Electromagnetic Coupling Issues to Watch Out for in High Frequency Silicon Design Wednesday, June 10

Karthik Srinivasan, Sr. Manager, Product Management Session title: Designing High-Speed Memories for the Edge Without Falling Over the Edge Wednesday, June 10

Karan Sahni, Director, Applications Engineering Session title: All things 3D-IC: Taking the Headache out of Managing Multiphysics Codesign for a 3D-Chip Package-System Thursday, June 11

Remember, it is a virtual event so register now and you will get a link to the replay in case you miss it. The SemiWiki bloggers will be all over this event so stay tuned for our expert observations, opinions, and experience on the subject matters.

I hope to virtually see you there!

Also Read

Prevent and Eliminate IR Drop and Power Integrity Issues Using RedHawk Analysis Fusion

Reliability Challenges in Advanced Packages and Boards

Thermal Issues and Solutions for 3D ICs: Latest Updates and Future Prospect

May 22, 2020July 18, 2025

Synopsys Announces IP Supporting 5G’s Game Changing Low Power IoT Spec

Synopsys Announces IP Supporting 5G’s Game Changing Low Power IoT Spec
by Tom Simon on 05-22-2020 at 6:00 am
Categories: 5G, Mobile, Synopsys

If you are like me, you will get a 5G phone because of the high bandwidth it offers. However, there is a lot more to 5G than just fast data. In fact, one of the appealing features of 5G is low bandwidth communication. This is useful for edge devices that perform infrequent and low volume data transfers and depend on long battery life. Prior to 5G many devices relied on 2G or 3G for data transfer which came with very high power requirements and costs, due to cellular overhead. 5G adds support for Narrow Band IoT (NB-IoT) communication for power sensitive devices.

However, simply taking a radio architecture designed for higher bandwidth and applying it to NB-IoT leaves a lot to be desired. The best analogy I can come up with is why SUVs initially drove like trucks. If you take a truck chassis and build an SUV on it, what you will get is a car that rides like a truck.

Synopsys does a good job of highlighting this in a recent webinar video that introduces their new NB-IoT ARC Communications IP Subsystem for Wireless Narrowband IoT designs. The video was done in conjunction with Santa Clara based Palma Ceia Semidesign who collaborated with Synopsys to develop a complete hardware/software NB-IoT Solution. Rich Collins, PMM at Synopsys for ARC Processors & Subsystems starts by describing what is new and different about 5G’s NB-IoT.

Rather than take a wide band cellular LTE modem and adapt it to NB-IoT, Synopsys has taken the approach of eliminating unnecessary hardware and moving much of the functionality into software running on a specifically designed processor. This has many advantages. There is a shortened development cycle for the smaller hardware implementation. It is also more flexible and can easily be adapted to changing standards. Synopsys provides a full software kit to support Base Comms and the NB-IoT User Equipment Stack.

The processor at the heart of this Subsystem is the ARC EM11D. It combines high efficiency control with ultra low power DSP operations. Its ARC Processor EXtension (APEX) mechanism is useful for adding application specific extensions in the form of hardware RTL. It features a single cycle 16+16 MAC that efficiently supports PHY data processing. There is also a development library with rich DSP functions.

The NB-IoT subsystem has many features that enable low power communications. The Digital Front End facilitates integration with RF transceivers. Viterbi and trig functions are handled in hardware through APEX instructions. There are standard AHB/APB busses that help with SoC integration. There are also standard peripheral interfaces that can be used for power management, as well as RF and host connectivity. The subsystem also possesses flexible power management features with customer programmable power modes.

Rich talks about the needs of a complete IoT SoC using their IP based system concept. The IoT comms subsystem is combined with tRoot HSM for iSIM to provide SIM functionality and security. An RF transceiver, such as the Palma Ceia PCS NB-IoT Transceiver, eFlash and RAM/ROM round out the system, providing everything needed for a fully functional IoT SoC that can use 5G networks and have standby battery life of over 10 years.

At the end of the webinar Rich discusses a demo platform they assembled that shows the feasibility of the complete solution. 5G NB-IoT will be used in medical/fitness devices, smart cities, smart agriculture, industrial automation and many other applications. With the roll out of 5G, NB coverage will be available in places that never had low cost and low power service. There is rapid adoption in the US, Europe and Asia. Undoubtably there will be a high demand for SoCs that support NB-IoT. I’d suggest the Synopsys/Palma Ceia webinar video to anyone who has an interest in this topic. It is available on the Synopsys website and goes into much more detail on the ARC Communications IP Subsystem and RF transceiver.

May 21, 2020October 3, 2020

Talking Sense With Moortec…See No Evil!

Talking Sense With Moortec…See No Evil!
by Tim Penhale-Jones on 05-21-2020 at 10:00 am
Categories: IP, Moortec

In the first of this blog trilogy, Talking Sense with Moortec…’Are you listening’, I looked at not waiting for hindsight to be wise after the event, instead make use of what’s available and act ahead of time.

There’s a Japanese maxim, depicting three ‘wise’ monkeys… Kikazaru, Mizaru, and Iwazaru, better known as ‘hear no evil, see no evil and speak no evil’. If they were developing SoCs, you wouldn’t want them on your team. They aren’t going to listen to what the monitoring fabric is telling them, they wouldn’t be able to see deep inside their device to understand what was really happening during device bring up or mission mode and they certainly aren’t going to tell you what they haven’t done or if something is wrong. You’ll be able to see that for yourself when your device comes back from the fab and it’s performance is below the spec’s requirements.

Sometimes turning a ‘blind-eye’ can work out OK. Take a famous nobleman from the Elizabethan times in Britain. Allegedly playing a game of bowls (Francis Drake Wikipedia Page) on Plymouth Hoe, (a few miles from Moortec’s Worldwide HQ), Sir Francis Drake, an English sea captain, privateer, slave trader, pirate, naval officer and explorer is alleged to have looked at the advancing Spanish Armada off the Plymouth coast and declared there was plenty of time to finish the game. The expression ‘turning a blind eye’ is originally attributed to Admiral Horatio Nelson, who used his injured blind eye when wishing to ignore instructions from his superiors in battle!

SoC development is a complex business. With shrinking geometries and escalating costs, trusting to luck is a dangerous strategy, especially when there are off-the-shelf solutions that will give you much greater visibility into your design.

So Mizaru isn’t a reliable engineer and Nelson and Drake did take the risk…yet there are a lot of casinos in Las Vegas who make a lot of money from those whose luck runs out. To quote Clint Eastwood in the film Dirty Harry, “You’ve got to ask the question: ‘do I feel lucky?’ Well, do ya, punk?”…with 5nm tape outs running to 10 figures, luck isn’t a viable commodity.

In case you missed any of Moortec’s previous “Talking Sense” blogs, you can catch up HERE

Watch out for final part of this blog trilogy which will be available in early June, keep and eye on our Social Media pages for more information!

About Moortec
Moortec have been providing innovative embedded subsystem IP solutions for over a decade, empowering customers with the most advanced monitoring IP on 40nm, 28nm, 16nm, 12nm, 7nm and 5nm. Moortec in-chip sensing products support the semiconductor design community’s demands for enhanced performance optimization and increased device reliability, helping to bring product success by differentiating the customers’ technology. With a worldclass design team, excellent support and a rapidly expanding global customer base, Moortec are the go-to leaders in innovative in-chip technologies for the automotive, consumer, high performance computing, mobile and telecommunications market sectors.

For more information please contact Ramsay Allen ramsay.allen@moortec.com, +44 1752 875130, visit www.moortec.com and follow us on Twitter and LinkedIn.

May 21, 2020March 25, 2022

Atos Crafts NoC, Pad Ring, More Using Defacto

Atos Crafts NoC, Pad Ring, More Using Defacto
by Bernard Murphy on 05-21-2020 at 6:00 am
Categories: Defacto Technologies, EDA, Events

I’ve talked before about how Defacto provides a platform for scripted RTL assembly. Kind of a rethink of the IP-XACT concept but without need to get into XML (it works directly with SV), and with a more relaxed approach in which you decide what you want to automate and how you want to script it.

They’re hosting a webinar on May 28^th 10-11am PDT (REGISTER HERE) in which Atos talk about how they use the tool in building a proof of concept for the MontBlanc 2020, a European HPC processor architecture.

This processor architecture is a scalable array of cores, interconnected through a NoC mesh connecting a crosspoint and protocol component at each core. This is a perfect application for the Defacto platform. All the design and architecture smarts are in Atos, however scripting assembly in SystemVerilog taking full advantage of parameterized interfaces can be very messy – as any designer script enthusiast knows. That’s where Defacto adds value, by handling that SV complexity while still allowing full freedom for Atos to script what they want.

The speaker (Laurent Marliac from Atos) mentioned that in their case, they can have up to 64 cross points in the mesh, each with up to 100 parameters to be configured, and each with complex configurable connectivity between cells in the array. Manually creating this in SV makes no sense and anyway isn’t the architecture/design value-add in the process. Defacto lets the design team define what they want through their own YAML scripts, from which they generate two Tcl files, one to drive RTL generation for the NoC top-level and one to drive generation of a testbench for that NoC. All the design intent and experience is in the Atos YAML scripts and their translation to Defacto Tcl or Python commands.

Once this scripting and flow has been set up, Laurent says that while figuring out what they want to change in the YAML takes thought and time, generation of a new NoC and testbench through the rest of the flow takes only a few seconds. Laurent also mentioned that they are using DeFacto not only for the NoC but also pad ring generation and DFT module generation, each of which has to scale flexibly as the processor array scales.

This makes a lot of sense to me. In fact I wish I’d thought of it when we were promoting GenSys at Atrenta (our somewhat equivalent tool). Scalable components like NoCs and scalable systems like the MontBlanc 2020 are perfect applications for an automation tool to connect designer/architect scripting to SystemVerilog RTL generation. The mistake we made was to try to own as much as possible of the generation flow, which really wasn’t possible given the complexity of product engineering, architecture and design needs.

Pad rings are a perfect example. We wanted engineers to fill out a highly complex spreadsheet to describe all the IO muxing, pad cell types and selection controls, but that’s impossible. Needs vary too widely even between product groups within the same company. Defacto doesn’t try to manage that part. Engineers can build their own spreadsheets and scripts, then let Defacto deal with the SV end of the problem.

For anyone planning to automate parts of their design construction, this will be a must-watch. Remember to REGISTER HERE to watch the webinar on May 28^th 10-11am PDT.

Also Read

Build Custom SoC Assembly Platforms

Another Application of Automated RTL Editing

Analysis and Signoff for Restructuring

May 20, 2020January 19, 2021

A Thoughtful Semiconductor Outlook – Needed Now More Than Ever

A Thoughtful Semiconductor Outlook – Needed Now More Than Ever
by Mike Gianfagna on 05-20-2020 at 2:00 pm
Categories: Semiconductor Services

If you’re not dizzy from all the changing market projections lately, you soon will be. At times like this, I believe it’s important to keep perspective and look beyond the next 24-hour news cycle to try and understand what the future holds. I’m happy to report there’s a great event coming up in June that will do just that.

The Silicon Valley chapter of SEMI is presenting a webinar entitled: WAFERS TO WALL STREET—A Semiconductor Outlook: Emerging Markets & Technologies and the Impact of COVID-19 on the Supply Chainon June 25, 2020 from 8:00 AM to 10:45 AM Pacific Daylight Time. This event looks like it will deliver a lot of great information. Before I get into that, a bit about the organizer.

In its words, SEMI is a “global industry association serving the product design and manufacturing chain for the electronics industry.” The organization has over 2,300 member companies and 1.3 million individual members. I’ve been to many SEMI-run events over the years and I can tell you they are relevant, well-run and informative.

The upcoming event promises to deliver an important and unique perspective. We all know the semiconductor industry is influenced by a complex balance of financial results, ecosystem interactions and market performance (both existing and emerging). You need to take all that into account to try and figure out what will happen next. This event brings together a panel of speakers that can address all those aspects. The top-level agenda of the event includes:

Market Outlook, Technology Trends, Market Indicators and Drivers
Impact of Emerging Technologies on Regional & Global Economies
Impact of COVID-19 on the Electronics Supply Chain
Trends for Fab Investments and Capacities
Materials and Advanced Packaging Opportunities and Challenges
Integration Technologies
Q&A Session

That’s a lot to deliver. Let’s look at who will be presenting:

Jan Gaudested: Vice President, Business Development, Wooptix, a light field imaging company headquartered in Tenerife, Spain, developing advanced technology for the semiconductor metrology equipment market.

John Pitzer: Managing Director, Global Technology Strategist, Technology Sector Head and Semiconductor Analyst for Credit Suisse Group. Mr. Pitzer has a lot of excellent credentials regarding the semiconductor capital equipment market.

Godfrey Cheng: Head of Global Marketing, TSMC. TSMC needs no introduction. Prior to TSMC, Mr. Godfrey led various corporate, product and technical marketing functions at ATI Technologies and AMD.

Wenge Yang: Vice President, Market Strategy, Entegris. Dr. Wang has been leading product and market strategy, market research and market trend analysis, strategic marketing, and the strategic technology roadmap for Entegris since 2012. Previously, he was an equity research analyst at Citigroup covering the semiconductor equipment and materials sector. Dr. Yang received a PhD in Materials Science and Engineering and an MBA from Rensselaer Polytechnic Institute.

Christian Gregor Dieseldorff: Senior Principal, Industry Research and Statistics Semiconductors, SEMI HQ. Before joining SEMI in 2007, Mr. Dieseldorff led engineering efforts at places like Siemens, IBM, International Sematech and Infineon.

Carolin Seward: Vice President & General Manager, Data Center Solutions Group, Intel. She is responsible for delivering integrated data center solutions with the best customer experience for the lifecycle of the product. Previously, Carolin was Vice President in the Technology and Manufacturing Group and Director of Global Supply Management at Intel.

Katsumi Hoashi: Vice President, Corporate Strategic Planning, TDK. Haoshi-san has 20 years of management experience in system LSI products in the consumer market. He has also worked at TDK, Socionext and Panasonic.

Yin Chang: Senior Vice President, Sales & Marketing, ASE Group Global. Mr. Chang is responsible for developing and executing sales strategy and marketing activities for ASE’s expanding packaging, systems, and integration solutions portfolio. He has a long history of working on advanced packaging technologies.

As you can see, all aspects of the forces that influence the semiconductor market will be covered at this event, from financial to equipment, ecosystem and technology/markets. Learn more about the event and sign up here. I plan to attend, and I hope you will as well.