I’ve talked before about how Defacto provides a platform for scripted RTL assembly. Kind of a rethink of the IP-XACT concept but without need to get into XML (it works directly with SV), and with a more relaxed approach in which you decide what you want to automate and how you want to script it.
They’re hosting a webinar on May 28th 10-11am PDT (REGISTER HERE) in which Atos talk about how they use the tool in building a proof of concept for the MontBlanc 2020, a European HPC processor architecture.
This processor architecture is a scalable array of cores, interconnected through a NoC mesh connecting a crosspoint and protocol component at each core. This is a perfect application for the Defacto platform. All the design and architecture smarts are in Atos, however scripting assembly in SystemVerilog taking full advantage of parameterized interfaces can be very messy – as any designer script enthusiast knows. That’s where Defacto adds value, by handling that SV complexity while still allowing full freedom for Atos to script what they want.
The speaker (Laurent Marliac from Atos) mentioned that in their case, they can have up to 64 cross points in the mesh, each with up to 100 parameters to be configured, and each with complex configurable connectivity between cells in the array. Manually creating this in SV makes no sense and anyway isn’t the architecture/design value-add in the process. Defacto lets the design team define what they want through their own YAML scripts, from which they generate two Tcl files, one to drive RTL generation for the NoC top-level and one to drive generation of a testbench for that NoC. All the design intent and experience is in the Atos YAML scripts and their translation to Defacto Tcl or Python commands.
Once this scripting and flow has been set up, Laurent says that while figuring out what they want to change in the YAML takes thought and time, generation of a new NoC and testbench through the rest of the flow takes only a few seconds. Laurent also mentioned that they are using DeFacto not only for the NoC but also pad ring generation and DFT module generation, each of which has to scale flexibly as the processor array scales.
This makes a lot of sense to me. In fact I wish I’d thought of it when we were promoting GenSys at Atrenta (our somewhat equivalent tool). Scalable components like NoCs and scalable systems like the MontBlanc 2020 are perfect applications for an automation tool to connect designer/architect scripting to SystemVerilog RTL generation. The mistake we made was to try to own as much as possible of the generation flow, which really wasn’t possible given the complexity of product engineering, architecture and design needs.
Pad rings are a perfect example. We wanted engineers to fill out a highly complex spreadsheet to describe all the IO muxing, pad cell types and selection controls, but that’s impossible. Needs vary too widely even between product groups within the same company. Defacto doesn’t try to manage that part. Engineers can build their own spreadsheets and scripts, then let Defacto deal with the SV end of the problem.
For anyone planning to automate parts of their design construction, this will be a must-watch. Remember to REGISTER HERE to watch the webinar on May 28th 10-11am PDT.Share this post via: