SemiWiki – Page 382 – The Open Forum for Semiconductor Professionals

June 2, 2020August 25, 2020

Arm Reinforces the Mobile Fortress

Arm Reinforces the Mobile Fortress
by Bernard Murphy on 06-02-2020 at 6:00 am
Categories: Arm, IP

Arm did it again. They continue to press their advantage, most recently with an announcement on their 2020 release of cores for mobile applications, in Cortex-A, in what they now call Cortex-X custom cores, in Mali GPUs and in the next generation of their Ethos neural net core.

Paul Williamson, VP GM of the client line of business, presented this release as necessary to keep up with the digital immersion that is rapidly becoming central to every aspect of our lives, from remote meetings, to education, to telehealth, to staying in touch with family and friends. For most of us, that interaction is through our phones. And of course, machine learning is becoming an integral part of that experience, for all the usual reasons – clever image processing and bio-sensing – but also for better managing the device, in power management and behavioral security.

Cortex-A78 is the latest high-end CPU, offering 20% higher performance in the same power envelope as A77 for a multi-day battery life, and in a 15% smaller area footprint over A77 in an octa-core cluster with A55.

Paul also announced the Cortex-X program, a way for partners to work with Arm on the customization option they introduced recently. Rather than a “here’s a way to add your custom instructions, good luck” approach, Cortex-X is a collaborative program in which partners work with Arm to develop differentiated and proven solutions with maximum performance as the primary goal. The first core in this class, developed with one or more partners (Paul wouldn’t elaborate) is called the Cortex-X1 and provides 30% sustained performance over the previous generation.

In graphics, Paul introduced the Mali-G78, with 25% better performance over the previous generation, support for up to 24 cores, new technology to improve scalability and reduce energy consumption and 30% reduction in energy for a key math unit, lowering total power consumption. There’s a big emphasis here in enhancing mobile gaming in rendering complex scenes like smoke, grass and trees. Arm has also put more into machine learning performance on the GPU, showing an average 15% performance increase over a variety of benchmarks.

Interestingly, Arm aren’t only pushing the premium experience in these devices. They have also introduced a Mali-G68 core for phones in the sub-premium tier, supporting all the features provided in the G78 but scaling up to 6 rather than 24 cores. Which should make it a lot easier on OEMs to support common software and a common experience against a range of phones. Sub-premium users can also play Fortnite, just a little slower.

I for one was happy when Arm introduced their first true neural net core in Ethos. It was a natural for them to have an offering in that space, and this also looks like it will be a dynamic player in the line-up. The second-generation core in the 2020 announcement is the Ethos-N78, offering double the MAC capacity, new compression technology to further reduce off-chip memory accesses per inference, along with more than 90 different ways to configure the core. Stats show 2X performance using full MAC capacity versus N77 and more than 40% DRAM bandwidth efficiency.

All in all, the king just took a big jump forward in mobile support. Arm was always a good solution provider, competition is making them better.

June 1, 2020August 25, 2020

TSMC Pushes out Equip Purchases – SIA and SEMI ask for Government Help

TSMC Pushes out Equip Purchases – SIA and SEMI ask for Government Help
by Robert Maire on 06-01-2020 at 9:00 am
Categories: China, Semiconductor Advisors, Semiconductor Services

TSMC pushing out equipment purchases
Covid/China trickles down to chip industry
SIA and SEMI ask for financial/govt help to keep up
The beginning of another down cycle?

We have heard from a number of sources that TSMC has started to push out equipment orders as concerns grow about the second half of the year.

Right now is the most logical time for TSMC to hedge their bets as they have rolled out all the needed/important purchases to get 5NM finished and get manufacturing up to speed to support their number one customer, Apple, in its launch of the Iphone 12 in the fall.

As we have pointed out many times, in a yearly, repeating pattern,TSMC starts ordering equipment in Q4, installs in Q1/Q2 to be ready for the Q3 Apple push. Any equipment ordered or due to be shipped now won’t help with the Iphone launch so its a good time to put the brakes on.

Covid & China trickle down to production
We have been saying for several months now that the second half of the year would get ugly as the double impact of Covid and China trade issues (Huawei) trickle down to demand and production of chips. The work at home economy won’t offset 25% unemployment and Huawei getting cut off. An initial surge of demand related to servers and laptops needed for work at home is more of a one time event rather than a sustainable, permanent increase.

Almost every equipment company we listened to on recent earnings calls was very cautious and unwilling to talk about the second half as everyone seems to agree, in an unspoken manner, that things will get worse.

Perhaps a bigger question is wether the memory industry will also slow down along with the foundry industry. There is obviously more sustainable demand for memory for servers and cloud based applications but will consumer slowing offset that?

Given that the memory industry is always a delicate game of supply/demand balance we think the current global events will likely drop demand below a critical level needed to support current pricing. Perhaps not across all memory types but enough to weaken pricing and thus slow spending again. We are not that far out of a sharp memory downturn which followed an unusually strong memory up cycle. We could be returning to more “normal” memory cyclicality.

WSJ reports that US chip makers are asking for help
The Wall St Journal, which has been paying a lot more attention to the chip industry, reported over the weekend that the US chip industry is asking for help in the face of foreign competition in the chip industry. Semiconductor Industry to Lobby for Billions to Boost U.S. Manufacturing

The semiconductor industry association (SIA) is looking for $37B in help to support the US industry. SEMI, the trade group for equipment and materials suppliers, is lobbying for tax credits rather than a direct cash handout.

This is of course coupled with Intel’s CEO, Bob Swan, directly lobbying Washington with plans for a US fab/foundry in competition to what TSMC is doing.

We hope that these proposals are taken seriously and moved on rather than ignored or watered down. As we have pointed out before, it is clear that semiconductor chips are more important than selling more soybeans (even though farmers may be in election battleground states and chips makers on the “left coast”).

China is pouring tens of billions of dollars, as quickly as possible into the crucial semiconductor industry and will obviously re-double efforts given the current debacle. Meanwhile, the US semiconductor industry has been exporting both technology and production.

These aid efforts aren’t likely to happen any time soon and may not happen until its too late but its certainly a good start, much like the US’s efforts with TSMC.

We think the odds of an investment tax credit are likely pretty good. Direct cash infusions are likely more difficult to get but the $10B or so needed for a bleeding edge fab is small change and may fit in existing defense budgets
The Stocks

We are likely to see a fall off but perhaps not as much in the near term as there has been so much positive momentum in the stocks and investors may not believe the weakness. We would expect the stocks to more fully capitulate in July when second quarter numbers are announced and the effects of the slow down will show up in black and white.

Although most in the industry are not giving official guidance, they have been doing everything but. They will have to more openly talk about the slowing orders.

Its clear that while TSMC may be the first to slow down, they will not be the last as these things are always industry wide, its just that some companies are smarter and react faster.

We also think that sooner or later the full impact of the Huawei issue will be felt as alleged “loopholes” get closed and the impact grows.

We think Applied has a lot of exposure to TSMC as does KLAC. ASML may be less impacted as most of the demand for 5NM related EUV tools has mostly been shipped. Lam is usually the memory “poster child” and also may have less near term impact if Samsung continues to spend.

Semiconductor Advisors

Semiconductor Advisors on SemiWiki

June 1, 2020January 27, 2022

Tortuga Logic CEO Update 2020

Tortuga Logic CEO Update 2020
by Daniel Nenni on 06-01-2020 at 6:00 am
Categories: CEO Interviews, Events, IP, Security, Tortuga Logic
2 Comments

We started working with Tortuga Logic two years ago beginning with a CEO interview so it is time to do an update. The venerable Dr. Bernard Murphy did the first interview with Jason which is worth reading again, absolutely.

Security is also one of the vertical markets we track which has been trending up for the last two years. In looking at the analytics Tortuga Logic has had a great couple of years as well but first let’s start with Jason’s official biography from the Tortuga website:

“Dr. Jason Oberg is Chief Executive Officer and co-founder of Tortuga Logic, where he is responsible for overseeing the company’s technology and strategic positioning. Dr. Oberg works closely with the Tortuga Logic team to facilitate capital, partnerships and revenue on all products and services. As a leading expert in hardware security, Dr. Oberg brings years of intellectual property and unique technologies to the company. His work has been cited over 700 times and he holds six issued and pending patents. He received his B.S. in Computer Engineering from UC Santa Barbara and an M.S. and Ph.D. in Computer Science from UC San Diego.”

Where did the company name come from?
The company was formed out of decades of hardware security research at UCSD and UCSB and we wanted to incorporate something aquatic (because both universities are on the ocean) and with something that represents protection and security. Tortuga (spanish for Turtle) was the conclusion because they live in the ocean and have a secure shell (you can see this on our logo). We of course chose Logic because we work closely with hardware. Hence Tortuga Logic was born.

Tortuga Logic is at a unique intersection of cybersecurity and hardware design. What security weaknesses is your company addressing?
Tortuga Logic is focused on identify digital issues in modern ASIC, SoC, and FPGAs that are either weaknesses in the logical design itself or the system firmware executing on the system. In general, the types of weaknesses we cover make up the majority (80%) of the existing hardware Common Weakness Enumerations (CWEs) list as maintained by MITRE.

What markets have the most at stake from a hardware security vulnerability?
Security is all about risk reduction, so the markets that have the most at stake financially are the ones that are the most sensitive to preventing hardware security vulnerabilities. From a semiconductor market perspective, a hardware vulnerability influences the security of the entire end system, so you must think vertically about the impact of hardware vulnerabilities.

That said, we see IIoT, Automotive, and Datacenters as being among the markets at the highest risk from a hardware vulnerability. These markets have felt the pain of recent hardware vulnerabilities in Bluetooth Low Energy IoT devices, Microarchitectural side channels in large application processors, and decentralized platform security in the datacenter to name a few. Aerospace/Defense is also a very important and sensitive market to hardware vulnerabilities, with the lowest tolerance for risk. Much of our technology has been DoD funded so there is a keen interest there.

What is driving the increase in hardware security vulnerabilities?
We really see 3 key factors contributing to this: 1) Modern SoCs are becoming increasingly more complex hardware software systems, 2) There’s been a surge of awareness around the ability to break into entire systems by finding hardware vulnerabilities, 3) Root of Trust initiatives, while extremely important and fundamental to building a secure system, are filled with mistakes primarily due to item (1).

Interestingly enough, as more focus is put into building security features deeper into hardware, the more attackers are focused on breaking them. They know if they can break the hardware barrier, they can then break into the system. Unfortunately, this is getting easier to accomplish given semiconductor devices are becoming so complex in both gate count and firmware.

How do does one place value on a security product, is it not like insurance?
Insurance really isn’t the right word, because security companies are not paying out claims after a vulnerability is found. That said, it is about financial risk reduction and being able to effectively measure the investments made against the reduced risk. Doing nothing puts you at the highest risk. If the cost of a vulnerability is extremely low, then doing nothing is probably fine because the financial risk is very low. However, the vast majority of markets the semiconductor market serves does have very high risk and thus investments in security do show measurable reduction in that risk.

Are there industry initiatives driving hardware security and how do you see them playing out over the next couple of years?
There are some very important initiatives that have recently started, and I highlighted one of them at the beginning of the interview. Specifically, MITRE in late February announced a taxonomy of common hardware weaknesses. The Common Weakness Enumerations (CWEs) have been used extensively by the software community to effectively classify the most impactful software weaknesses.

This new release 4.0, driven initially by Intel and MITRE with contributions from our security team at Tortuga Logic, allows for effectively capturing the most impactful hardware weaknesses. This is an important initiative because it will allow the industry to more transparently state what are the highest impact hardware weaknesses and suggested mitigations. This will allow everyone to build more secure systems and provide more transparent techniques for measuring effectiveness.

About Tortuga Logic
Founded in 2014, Tortuga Logic is a cybersecurity company that provides industry-leading solutions to address security vulnerabilities overlooked in today’s systems. Tortuga Logic’s innovative hardware security verification solutions, Radix™, enable System-on-Chip (SoC) and FPGA design and security teams to detect and prevent system-wide exploits that are otherwise undetectable using current methods of security review. To learn more, visit www.tortugalogic.com or contact info@tortugalogic.com.

Also Read:

CEO Interview: Robert Blake of Achronix

Flex Logix CEO Update 2020

CEO Interview: Jason Xing of Empyrean Software

May 31, 2020August 25, 2020

Misunderstanding the Economic Factors of Cybercrime

Misunderstanding the Economic Factors of Cybercrime
by Matthew Rosenquist on 05-31-2020 at 6:00 am
Categories: Security
1 Comment

A new study by Cambridge Cybercrime Centre titled Cybercrime is (often) boring: maintaining the infrastructure of cybercrime economies concludes that cybercrime is boring and recommends authorities change their strategy to highlight the tedium in order to dissuade the growth of cybercrime.

Warning: Full-blown rant ahead, as I am frustrated with reports such as this!

Limited focused research, which does not look at the big picture as it evolves, leads readers to poor conclusions that are oversimplified and not couched in reality.

Do these researchers really think that cybercrime is driven by motivations about it being sexy, a fun work environment, or exciting? This report suggests that if we market cybercrime roles as being tedious, then people will not go down that path. Ha!

Wake up! The vast majority of cybercrime is motivated by personal financial gain. Period. Additionally, the massive number of new followers of digital crime won’t care about tedium or the opinions of people that live a lifestyle where convenience plays a significant role in how to put food on the table.

Throughout history organized crime has aligned to a pyramid model where the greatest number of participants are at the bottom, doing grunt jobs. They are poorly compensated, take on more risk, terribly treated, and generally suffer in their daily grind. Most don’t aspire to be there, rather they do it because there are not better options.

This report misses the bigger picture!
Consider that one million people join the Internet every day. The majority of the next billion that will come online will be from economically struggling regions where people hustle to scratch a living every day. Unemployment is high and there are almost no opportunities to make money. Half the world makes less $10 a day and over 10% live on less than $2 a day. Even a basic job as a mule, social engineer, CAPTCHA reader, ransomware distributor, phishing scammer, etc. will make many of these people more money than they could otherwise. The people in warehouses that support click-farming, earning pennies, aren’t there because they want to be. They simply don’t have many options to earn a wage. They do what is necessary to subsist. Much of the next billion people joining the internet will see connectivity as a doorway for more opportunities to stay afloat.

Unfortunately, cybercrime will see an explosion over the next few years as people with the greatest needs see the Internet as an opportunity to sustain their family. Some estimates are as high as $6 trillion in overall impact. Cybercrime-as-a-Service is positioned for tremendous growth as it allows for people to join the support base of online criminal groups, without any requirements for hacking skills. The pay is low and the work is grinding, but the rewards may far exceed what is available to them otherwise. It does not matter if law enforcement communicates that such roles are boring for the majority of those joining the bottom ranks.

Discussions from people, in economically wealthy countries, about tedium is irrelevant and myopic when the greater scale is evaluated. For many millions of people, cybercrime will be an avenue for subsistence. For these people, the economics of survival and scarcity of alternative opportunities will drive decisions. This is the realistic risk we must address.

Image by Colin Behrens from Pixabay

May 29, 2020August 25, 2020

Time for Chip Diplomacy

Time for Chip Diplomacy
by Terry Daly on 05-29-2020 at 10:00 am
Categories: China
15 Comments

An industry caught in the crosshairs of geopolitics needs global emeritus leadership

The semiconductor industry is at the epicenter of great power politics. An ascendant China is on a quest for a unified global system with China as the leading power. The United States seeks to maintain its position as leader of the liberal democratic order and arbiter of the global economy. The flash points span trade, human rights, national security, and digital technology leadership. Can chip firms protect decades of investment and navigate access to China’s lucrative market under increasing US constraints?

The semiconductor industry and China are deeply integrated. As China captured roughly 50% production share of global electronics, chips became its leading import. China became “coupled” through its position in the global supply chain. Chip companies beat a path to China’s door for access to its fast-growing indigenous market and multi-billion-dollar subsidies. Intel, ARM and AMD formed joint ventures. Samsung, SK Hynix, TSMC, UMC, GF and Intel built 300mm fabs on the mainland. A vibrant Chinese communications sector (Huawei, ZTE, Xiaomi, Oppo, Vivo) consumed high volumes of chips from Qualcomm, Broadcom, Qorvo, Skyworks, Micron, and others. HiSilicon leveraged IP and design services from the industry and manufactured its chips in Taiwan using TSMC’s leading-edge technology. China established venture funds to invest in global firms and sent legions of engineering students to foreign universities. Chinese firms joined Industry Associations (SIA, GSA, SEMI, IEEE) to build relationships, acquire IP and influence standards. China was projected by SEMI (pre-COVID) to become the largest market for semiconductor equipment suppliers by 2021, powered by its “Made in 2025” strategy and push for self-sufficiency in chip production.

But there was a long-standing undercurrent of abusive business practices by China including IP theft, forced technology transfers, “pay-to-play” schemes and disregard of WTO obligations. The US pressed for remediation by leveraging tariffs, Huawei 5G security concerns and CFIUS expansion. Then, tragically, came COVID-19. Calls for “de-coupling” grow in frequency and volume. But modifying supply chains in a capital-intensive industry is not simple. Fabs are rarely “relocated” and replacing capacity is expensive. Moving design centers leads to dismantling high-performance design teams central to product development and customer relationship management. Firms face the loss of billions of dollars in revenue and profit along with significant market share by being blocked from access to China’s demand.

How can a firm best optimize shareholder value in this environment? The default of complying with US policy carries potentially severe economic and shareholder value impact. A recent BCG study highlights a loss of 37% in revenue and 18-points in market share for US firms in a 100% de-coupling scenario. Firms can exit non-strategic investments, migrate asset-lite missions to alternate geographies and modify plans for future capacity (e.g. TSMC in Arizona). They can change country of incorporation through merger with a foreign entity (inversion) or divest assets to a “friendly” foreign company with broader freedom of action to address China’s market. These strategies must survive oversight of the Foreign Investment Risk Review Modernization Act (enhanced CFIUS); each carries economic and political risk.

Global emeritus leaders (CEOs, CTOs, academia, government) and Industry Associations must play a more effective role in protecting the interests of the semiconductor industry. Advocacy efforts to-date have fallen short. A public “chip diplomacy” initiative could marshal respected industry emeriti to leverage their global networks and build a compelling picture of the benefits of an open and vibrant industry model. They could help parties envision the benefits of applying the emerging technologies of AI, IoT, blockchain, 5G and quantum computing to shared societal issues such as hunger, climate, and health. They could provide a technology roadmap enabling US-China commercial collaboration in space and sea exploration. Technology solutions to safeguard critical IP, reduce cyber threats and verify end-application use of commercial technologies could be defined. Revisions to the Wassenaar Arrangement governing export controls could help both countries address concerns. Confidence building measures and multilateral support (South Korea, Japan, EU) are critical.

Industry Associations could sponsor a series of “chip war games” to underscore the adverse outcomes of sequential escalation. One scenario might find China withholding shipment of precious metals, revoking licenses to do business in China, threatening market access to South Korea, Japan and other South East Asian countries and nationalizing the semiconductor assets of foreign companies. It could threaten military occupation of Taiwan and control of its vibrant chip sector. The US might in turn sequentially terminate visas for Chinese students, revoke licenses from Chinese companies doing business in the US and expand tariffs on a range of Chinese imports. It could supplement the denied parties lists and broaden the foreign direct product rule (a.k.a. Huawei chip ban) into a full-throated technology embargo, including semiconductor equipment, licenses to design tools and IP and the shipment of chips, denying China access to the lifeblood of its digital economy.

The case for de-escalation is clear. The desired semiconductor industry model is one of open markets, free trade, IP protection, full leverage of geographic competencies, innovation by a multi-cultural workforce, global collaboration in research and standards, all funded by private equity and efficient global capital markets. The US and China need to walk back from the precipice, stand-down the acerbic rhetoric and resolve issues underlying the battle for digital technology supremacy. Perhaps a truce on chips and a “co-opetition” model can pave the way for progress on the other bi-lateral flash points. A tall order, but a preferable outcome to mutually assured destruction of the industry and our nations.

Individual companies must take actions required to protect and optimize shareholder value. But if there were ever a time for global semiconductor emeritus leaders and Industry Associations to cash in on their decades of well-earned global relationships and activate chip diplomacy, it is now. We need both the US and China at the table. The stakes are too high to stand idly by and let the chips fall where they may.

Terry Daly is a retired semiconductor industry executive

May 29, 2020January 21, 2021

Minimizing Power Consumption in Ultra Low Power MCU Based SoCs

Minimizing Power Consumption in Ultra Low Power MCU Based SoCs
by Tom Simon on 05-29-2020 at 6:00 am
Categories: Dolphin Design, EDA, IoT, IP, Mobile

When it comes to extremely power sensitive applications such as IoT and edge devices, there is literally an arsenal of power saving techniques that could be used. The tricky part is figuring out which ones to use and how to use them for maximum benefit. This is coupled with the need to not hamper device performance or functionality. The trend is for increasing use of Ultra Low Power 32-bit microcontrollers (ULP MCUs) in SOCs for devices such as industrial instrumentation solutions, industrial controllers, connected home consoles, thermostats, temperature sensors, smart meters, smart grids, blood glucose meters, heart rate monitors, implantable devices, and IoT devices.

The range of possible power reduction techniques go from device and cell level to block and chip level, including mixed Vth cells, body biasing, thick oxides, clock gating, power gating, frequency scaling, always on domains, etc. Some of these techniques can be applied once during design and can be ‘forgotten’. Others need intelligence of their own to help manage them in conjunction with chip operation. Dolphin Design has recently published a white paper that does a good job of reviewing traditional and new power management techniques and discussing how they can and should be applied. The paper is titled “Breaking new energy efficiency records with advanced power management platform. “

Dolphin Design cites reports that show the ULP MCU market growing from $4.4B to $12.9B from 2019 to 2024. Many of these ULP MCUs will support analog mixed signal IoT devices that will have very complex operation modes and need to operate for weeks, months or years on a single batter or charge.

The white paper takes a look at various methods of power management, starting with off-chip PMICs, then progressing to on-chip Power Management Units (PMU) and programmable PMUs. Moving from a discrete PMIC to an on-chip power management approach reduces the BOM and permits tighter integration of power management functions. One drawback of on-chip software based power management is that the processor needs be ‘always-on’ which makes it a power sink, especially for chips that spend significant time in sleep modes. The alternative is to design FSM based logic that can provide most of the functions needed for power management, with reduced power consumption. Yet, FSM based PMUs are not as flexible

Dolphin Design describes their comprehensive power management solution Spider in their white paper. Their approach uses a power controller called MAESTRO, which is fully configurable IP that works like a state machine, but can but reprogrammed in the field if desired.

But there is a lot more to it. Dolphin Design have a comprehensive set of regulator IP that are extremely efficient at converting battery and supply voltages to on-chip logic levels. They are configurable as well, providing flexibility. Dolphin Design talks about their ultra-low leakage IP that are used for the always-on blocks. These include LDOs, dedicated oscillators and power gating solutions. The white paper also mentions PowerStudio, their GUI for configuring and controlling their low power elements. PowerStudio helps to verify the power management system as well. It offers a wide range of checks that cover power mode transitions, ICU responses, power mode coverage, ICU states, regulator model consistency, isolation, isolation control and retention.

The last portion of the white paper talks about benchmarking power consumption and efficiency. ULPMark-CoreProfile (ULPMark-CP) considers leakage current in sleep modes and active mode power consumption. Unlike peripheral power usage, MCU power varies significantly depending on the efficiency of the power management techniques that have been applied. Dolphin Design offers detailed results of benchmarking that compares the approaches mentioned above. From the baseline external PMIC to full utilization of all the methods that Dolphin Design supports there is a 2 orders of magnitude improvement of the ULPMark-CP numbers.

The Dolphin Spider platform promises to be extremely useful and efficient for the needs of ULP MCU designs. There is no doubt that the need for more efficient and longer life battery-based devices will continue to expand. Eliminating unneeded power consumption is the most cost-effective way to meet these market requirements. The full white paper is available on the Dolphin Design website and makes interesting reading on how a comprehensive power management system can deliver impressive results.

May 28, 2020October 3, 2020

PLDA Expands Data Interconnect IP Solutions with CXL and Gen-Z Protocol Support

PLDA Expands Data Interconnect IP Solutions with CXL and Gen-Z Protocol Support
by Mike Gianfagna on 05-28-2020 at 10:00 am
Categories: IP, PLDA

A couple of months ago I introduced PLDA, a new member of the SemiWiki community, with a post about PLDA’s switch IP and its support for PCIe and NVMe solid state disks. Working in the area of high-performance data interconnects requires support for a growing list of standards, standards that continually evolve. The trick is to stay at the leading edge of these standards so support is available early in the design process.

A recent press release from PLDA illustrates the company’s commitment to emerging standards. Entitled PLDA Announce Complete Support for CXL™ and Gen-Z™ protocols, the announcement has a back-story worth mentioning.

First, let’s look at the CXL protocol. Compute Express Link (CXL) is a new high-speed interconnect specification that focuses on CPU-to-device and CPU-to-memory applications. The technology maintains memory coherency between the CPU memory space and memory on attached devices, which improves performance and lowers complexity and cost. The spec is being developed by an open industry standard group formed by some very prestigious companies.

Gen-Z is a new data-access technology that offers low-latency for data and devices through direct-attached, switched or fabric topologies. Gen-Z fabrics utilize memory-semantic communications to move data, which minimizes overhead. Gen-Z is also developed by an industry consortium that has its own A-list members. Some of you may be wondering what memory-semantic communications is. The consortium posted this on Twitter to help: “What is memory semantic fabric? Communication at the speed of memory. A comm protocol that speaks the same language the CPU speaks”.

The goal of standards like CXL and Gen-Z is to enhance communication between compute and main memory to support more complex storage structures within and across systems. For further reading, this article sums it up as follows: “It will be hard to tell the difference between a system and a cluster … where there are memory servers, compute servers, and storage servers, all glued with a Gen-Z fabric into a very memory centric cluster.” Looking at the two standards, there is no Gen-Z without CXL. As these standards are deployed, Gen-Z will be bridged to CXL to extend CPU reach beyond the compute node, in composable data centers for rack/row/long-haul communication. Gen-Z expected to replace Infiniband in this scenario.

There’s one more important development to mention. On April 2, 2020, the CXL Consortium and the Gen-Z Consortium announced a memorandum of understanding. In an ecosystem that is characterized by highly competitive and secretive behavior, it is noteworthy that these two organizations decided to collaborate for the greater good. As stated in the announcement, “The MOU outlines the formation of common workgroups between both organizations to provide clear cooperation, defining bridging between the protocols while leveraging the strengths of both technologies.”

It is against this backdrop that the recent PLDA press release was made. Thanks to the clarifications provided by the MOU, PLDA is committed to support both protocols, with a focus on CXL IP first.

XpressLINK CXL is a parameterizable soft IP controller designed for both ASIC and FPGA implementation. The XpressLINK Controller IP leverages PLDA’s silicon-proven XpressRICH Controller for PCIe 5.0 architectures. The IP includes:

Support for the CXL 2.0 specification
Implementation of the CXL.io, CXL.mem, and CXL.cache protocols
Support for all three defined CXL device types
Support for the PCI Express 5.0 Base Specification, Revision 1.0
Support for the PIPE 5.x specification with 8-, 16-, 32-, 64-, and 128-bit configurable PIPE interface widths

Regarding availability, PLDA’s current XpressLINK CXL roadmap extends from the second half of 2019 to the first half of 2021. This aligns well with the roadmap of processor vendors like Intel. PLDA is already engaged with early adopters for this technology.

“The announcement of the MoU between the CXL and GenZ Consortiums is a key event in the IP Market as it paves the way to the future architecture of high speed interfaces,” said Arnaud Schleich, CEO of PLDA. “As an historic actor in this Industry, it was logical for PLDA to expand its product line to include both protocols and we are proud to be committed to pushing this evolution to the next level.”

Gen-Z early silicon is not expected before the second half of 2022. As stated by Gen-Z Consortium Chairman Kurtis Bowman in April 2020: “… Gen-Z early adopters will be coming online in 2022 and it will be mainstream by 2023 to 2024….”). PLDA’s roadmap for Gen-Z IP begins in 2021, but the company already demonstrated a proof of concept of their Gen-Z at SuperComputing 2019.

Supporting two emerging, complex protocols at the leading edge is not easy. PLDA appears to have done a great job here. For more information on this new standards-based IP, you can visit PLDA’s CXL IP webpage or PLDA’s Gen-Z IP webpage.

May 28, 2020August 25, 2020

What a Difference an Architecture Makes: Optimizing AI for IoT

What a Difference an Architecture Makes: Optimizing AI for IoT
by Bernard Murphy on 05-28-2020 at 6:00 am
Categories: AI, EDA, Siemens EDA

Last week Mentor hosted a virtual event on designing an AI accelerator with HLS, integrating it together with an Arm Corstone SSE-200 platform and characterizing/optimizing for performance and power. Though in some ways a recap of earlier presentations, there were some added insights in this session, particularly in characterizing various architecture options.

Accelerator Design

Mike Fingeroff kicked off with high-level design for the accelerator, showing a progression from a naïve implementation of a 2d image convolution with supporting functions (eg pooling, RELU) in software. This delivered 14 seconds per inference where the final goal was 1 second. His first goal was to unroll loops and pipeline. New here (to me at least) is that Catapult generates a GANTT chart, giving a nice schedule view to guide optimization. So Mike unrolls and finds he has memory bottlenecks, also highlighted by a Silexica analysis. Not surprising since he’s using a 1-port memory, again with naïve reads and writes. He switches to a shift-register and line-buffer architecture supporting a 3×3 sliding window in convolution and the bottleneck problem is solved. He also looks at Silexica analyses to decide how/if to buffer weights. Now he’s down to just over a second per inference with bias, RELU and pooling still in software (running on the embedded CPU).

Then he runs Matchlib simulations for a more comprehensive analysis (couple of hours) and find some outliers, such as one inference taking 4 minutes, principally caused by delays in CPU computations. He pushes these software functions into the hardware (which adds little overhead) and that problem goes away. While he’s met the performance goal, Mike also talks briefly about ways to further increase performance, through added output parallelism (compute 2 outputs per cycle) and input parallelism (fetch and compute on 2 inputs per cycle since the input bus is 64bit and he only wants 32bit accuracy in the inference).

Arm subsystem integration

Korbus Marneweck from Arm followed, introducing Arm IoT solutions with Corstone (the Mentor demo is integrated into this platform). Corstone provide reference designs for secure IoT implementation, with TrustZone, security IP and lots of other goodies and setup for an easy path for PSA certification. There’s quite a lot more detail on Corstone which I’ll skip in the interest of quick read. Korbus did talk about method to connect an accelerator, through a memory-mapped path, as a co-processor or through custom instructions. That raised some Q&A on working with custom instructions which may be interesting if you want to dig deeper into the video.

Characterization

Russ Klein took the last part of the presentation, talking about integrating this all together and especially characterizing for performance, area power/energy per inference. This for me was the most interesting part of the talk because it puts hard numbers behind the benefits of an HLS-based approach to designing these AI accelerators. Quick clarification here, they measured characteristics just for the implemented accelerator, not the Corstone subsystem. However within the accelerator they are running full implementation (based on Mentor tools) and using parasitics from that implementation. The table opening this blog shows the results.

The first row is for a very naïve software-only implementation using floating point. That’s just a reference for grins. The second uses integers rather than floating point, delivering ~10 minutes/inference at ~5 joules/inference. First pass unoptimized CNN plummets to ~50 seconds and 800mW/inference. Windowing (shift registers and line-buffers) drops to 9 seconds and 135mJ/inference. Analysis continues through various combinations: parallel out, moving the RELU etc. functions into the kernel and parallel in, until they get down to 8-bit data running through a quad convolver deliver a quarter second and 6mJ per inference. That’s a lot of architecture options they explored, all enabled by starting with an HLS model and looking at tradeoffs in pipelining, windowing, memory architectures and input and output parallelism. None of that feasible on the network model side (which doesn’t understand hardware constraints and options) or on the RTL side (which would be impossibly painful to keep rearchitecting.

Good stuff.

You can check out more on this topic through Mentor’s on-demand webinars. See for example their webinar on sliding window memory architecture for performance.

May 27, 2020September 30, 2020

The Growing Relevance of IP-XACT in Today’s Complex Designs

The Growing Relevance of IP-XACT in Today’s Complex Designs
by Ranjit Adhikary on 05-27-2020 at 10:00 am
Categories: EDA, Magillem

The life of a SoC designer is an unenviable one. Not only does he have to work in a landscape where competition is intense but he also has to collaborate effectively with globally dispersed teams to ensure the design meets the project timeline. Then there are also the risks, more so in the current pandemic! There is the constant fear of a dead chip on arrival or issues found post silicon or the tape-out slipping beyond the due date which can have widespread ramifications. As part of a multi-pronged strategy to mitigate the risks as well as build designs faster, a large number of companies have slowly but steadily moved towards using verified third-party IPs, for parts of the design which is not in their core competency.

However, this trend of incorporating more and more third-party IPs in an SoC is not without its share of problems. The complexity of IP configurations now is no longer easy to manage manually and requires an infrastructure which is capable of tracking the configurations throughout the product life cycle. The tight marriage required between the hardware and software teams to provide state-of-the-art SoCs of today adds yet another dimension to the challenges faced by the designers. The need for a methodology to build, update and configure IPs appropriately is felt more so than ever. While there are some software solutions which address this aspect of the problem to some extent, their reliance on proprietary technologies and inability to coexist with legacy flows poses a problem for a large number of companies.

Over the last half decade, companies have slowly embarked on an effort to addressing these issues and automating flows while relying on standards as an underlying infrastructure and ensuring a common data-model which can be leveraged between all the teams.

It is no mere coincidence that most enterprises have chosen IP-XACT as the underlying standard to base their infrastructure for developing automated flows.

What is IP-XACT?

IP-XACT, first released by the SPIRIT Consortium, is a standard developed with the sole objective of promoting reusability of IPs within the design community. It enables IP providers to provide a singular description of their IPs which is both readable and machine processable for both components and designs, and share it with the IP users packaged along with the desired collateral. IP-XACT also describes system designs and the interconnection between the IPs along with other details such as address maps, interfaces etc. providing a common design representation that can be used by IP vendors, design integrators and EDA tool providers to exchange within their flows.

IP-XACT became an IEEE standard in 2009 and is published as IEEE-1685. While a number of companies started using it even before it became an IEEE standard, the usage started increasing in the last few years as more and more companies realized the potential it offered in helping create and automate their custom design flows.

Why the sudden increase of interest in IP-XACT?

With a lot riding on the SoCs of today, both small and large semiconductor companies alike, are heavily invested in the common goal of ensuring successful tape-outs within the scheduled timelines. Any delays or snags in the design flow can potentially impact both their time-to-market as well as the company bottom line.

Most design teams have attempted to resolve this issue by working in parallel on several fronts and investing heavily on block and system-level verification. For example, top level and block level design integration of designs is done in parallel to the development of RTL and verification environment. But this approach is not the most optimal often requiring more resources and prone to manual errors.

Another issue which designers face involves the EDA tools produced by a number of vendors, many of which use unique and proprietary formats. Developers are often posed with the problem of identifying ways to exchange the design information efficiently between different design environments.

One way to resolve this and ensure timely and successful tape-outs is to provide for a solution, which encompasses at the very least:

A well-defined design methodology suited for your custom requirements and EDA tools of your choice
Efficient design collaboration between design teams sometimes dispersed across geographical boundaries especially between hardware & software teams
Leverage IP reuse for internal and third-party IPs
Design flow automation which ensures
- Faster design integration
- Selecting the correct configuration of IPs
- Smooth exchange of design information between different tools and ensuring design handoffs between teams
- Avoiding misinterpretation of design specifications such as register maps
- Automatic generation of RTL and other collateral such as C header files, memory maps, UVM models, documentation etc.

In the past, companies have tried to address some of these problems, by creating solutions based on either custom scripts, proprietary technology or a combination of both. The challenge with this approach has been that the solution needs to be constantly maintained and tends to fall apart when the engineers managing the solution leave the company. The ability to integrate design flows by creating custom generators to pilot EDA tools and back annotate the results has resulted in companies now taking a hard second look at IP-XACT to serve as the underlying vehicle for their tooling solutions. IP-XACT stands out in being an IEEE standard, which means that companies no longer have to worry about maintaining or enhancing any proprietary infrastructure. By providing a standardized data exchange format, IP-XACT has the flexibility to represent multiple companies’ requirements and the hooks to allow design information to be automatically extracted and used in flow automation and advanced verification.

One of the important cornerstones of the IP-XACT standard is its capability of packaging a design into an IP-XACT component. The component description includes among other things, the specification of the periphery of each IP block along with the bus interfaces, physical signals, their mapping to logical bus interfaces, configuration, address blocks, register descriptions, filesets and documentation information. The information contained in the description can be used by designers to automatically integrate the correct configuration of IPs and construct the SoC faster in a single integrated design and verification environment while mitigating the possibility of any errors being introduced in the design.

An inherent advantage of using IP-XACT is that it not only helps in improving the IP ecosystem within a company as design teams can easily package a design along with the necessary collateral, but its use as a common data model also enables distributed teams to collaborate more efficiently and exchange design information quickly between different design environments. IP-XACT also comes equipped with a standard API which can be used to customize solutions even further by complimenting the IP-XACT description with a layer of software. For example, the API could be used with an EDA tool to actually interface into a customer flow by leveraging the design information available in the IP-XACT database. Using the API, embellishes the value proposition of the generators and can be used to capture the configuration intelligence within the generators to automatically generate the final configured IP-XACT description of an IP. This capability is of immense value to an IP provider as it enables a precise and controlled use of the selected configuration.

The versatility of the IP-XACT standard and its ability to coexist and work with other systems including legacy ones used for IP reuse and flow integration, makes it the perfect choice for many a company.

Advantages of using IP-XACT

One of the most important aspects of IP-XACT is that it is an IEEE standard backed by leading semiconductor companies who are heavily invested in utilizing it for tooling purposes as well as IP reuse. The fact that it is developed keeping IP reuse in mind, makes it ideal to build IP ecosystems within an enterprise.

Design teams can leverage this ecosystem by using it to create more IP sub-systems and SoCs. To assemble the designs faster, designers can use the connectivity features defined in IP-XACT to quickly create an interconnect fabric for their designs and utilize the register maps of the IPs to compute the full system memory map of the design. Designers can also use the design database to create generators such as s/w C header files, netlist in VHDL, Verilog, System Verilog or System C, UVM models, testbenches, documentation etc.

One of the lesser known advantages of IP-XACT and one of the most important capabilities is that it can be used extensively for tooling purposes and automating the flows, something which a number of companies have started to capitalize on of late.

Some of the other capabilities which IP-XACT possesses includes

IP-XACT is designed for IP reuse
Faster and easier system integration
- Support for multiple layers of abstractions (designs and protocols) enables integrators to quickly create the top level for the designs.
- Built in error checks reduces the possibility of errors
Extensibility to add design and flow information
With support for features such as views/fileSets,, managing deliverables becomes simple and fully automated process.
Support for design traceability which is a key requirement for ISO 26262 certification

A standard does not have to be perfect but if there are enough people adopting it over time, it can be considered to be a good standard. This applies to IP-XACT as well. With the number of companies adopting the standard increasing steadily, there is no doubt that the standard is here to stay.

Finding the right solutions

To hasten the process of developing the SoC or IP, it becomes necessary to use solutions which are tried and tested and is part of a production flow in several companies. For more information on how to build your designs faster, visit www.magillem.com. Magillem customers include the top 20 semiconductor companies worldwide.

Magillem is a pioneer and the leading provider of IP-XACT based solutions aimed at providing disruptive solutions by integrating specifications, designs & documentation for the semiconductors industry. Using the solutions provided by Magillem, design companies can automate their design flows and successfully tape-out their designs faster at a reduced cost.

It is one of the leading authorities on IP-XACT standard. Magillem is the Co-chair of the IP-XACT 2021 Accellera committee and an active member since the inception of the IP-XACT standard.

May 27, 2020May 4, 2022

Is the Worst Over for Semiconductors?

Is the Worst Over for Semiconductors?
by Bill Jewell on 05-27-2020 at 6:00 am
Categories: Semiconductor Intelligence, Semiconductor Services

The worldwide economic outlook is chaotic due to the ongoing COVID-19 pandemic. The outlook for the semiconductor market is also very uncertain. 1Q 2020 revenue versus 4Q 2019 was mixed for major semiconductor companies, ranging from a 19% decline for STMicroelectronics to 9.9% growth from Kioxia (previously Toshiba Semiconductor). WSTS reported a decline of 3.5% for the semiconductor market in 1Q 2020. Guidance for 2Q 2020 revenues shows continued caution. Most companies expect a decline in 2Q 2020 revenues from 1Q 2020.

The range of 2Q 2020 guidance is wide. Low end 2Q 2020 guidance from Qualcomm, Texas Instruments, STMicroelectronics and NXP Semiconductors ranges from -14% to -22%. The upper end guidance for these companies ranges from -7% to -0.3% and the midpoint guidance averages -10.5%. Seemingly optimistic guidance from Nvidia and Infineon is deceptive. Nvidia began to include the revenue of its Mellanox acquisition in 2Q 2020. Excluding the effect of the Mellanox acquisition, the midpoint of Nvidia’s 2Q 2020 guidance would be about 4% instead of 18.5%. Similarly, Infineon is including revenue from its Cypress Semiconductor acquisition in 2Q 2020. Excluding Cypress, the midpoint of Infineon’s guidance would be about -13% instead of +5.7%.

The memory companies (Samsung, SK Hynix, Micron and Kioxia) generally had positive 1Q 2020 revenue growth compared to 4Q 2019. The midpoint of Micron’s guidance for its fiscal quarter ending later this month is +2.1%. Samsung, SK Hynix and Kioxia did not provide revenue guidance for 2Q 2020, but they all expect strong demand from PCs and servers but declining demand from smartphones.

PC demand is expected to be strong as many more people are working from home or receiving educational instruction from home. Increased dependence on the internet for communication and information is driving continued growth in servers for data centers. IDC in March forecast a 9% decline in PC and tablet unit shipments in 2020 based on weakness in the first half of the year and a pickup in the second half. IDC reported 1Q 2020 PC unit shipments declined 9.8% from a year ago, following three quarters of year-to-year growth in 2019.

Smartphone demand in 2020 is more uncertain. IDC in March forecasted a 2.2% decline in smartphone unit shipments for the year. In April, Strategy Analytics projected a 23% decline. IDC reported 1Q 2020 smartphone unit shipments were down 11.7% from a year ago. Although many experts expect weak smartphone demand in 2020, sales could be driven by increased use of video communication. Just as businesses are using video conferencing on PCs to increase communication among remote employees, households are increasingly using video over smartphones to communicate with family and friends they cannot visit in person. This increased use of video may prompt many to upgrade their smartphones.

1st quarter 2020 electronics declines were primarily due to supply issues. China electronics production was down significantly in January and February as China shut down much of the country in an effort to contain COVID-19. January and February 2020 China electronics production value in yuan was down 13.8% from a year ago. Unit production of PCs was down 29% and mobile phone unit production was down 41%. China production value has since recovered, with March up 9.9% from a year ago and April up 11.8%. PC unit production was up 29% in April versus a year ago. Mobile phone unit production has yet to return to previous levels, with April down 26% from a year ago.

Electronics markets for the remainder of 2020 will be driven by demand. For the second quarter, most of the world was under stay-at-home orders (or recommendations) for the month of April. Many countries are beginning to open up in May and continuing into June. Economic activity should continue to pick up in 3Q 2020 and 4Q 2020 barring a significant reemergence of COVID-19. 2021 should be a strong growth year as the economy returns closer to normal and pent-up demand drives increased spending by consumers and businesses.

Recent forecasts for the semiconductor market in 2020 vary widely, as can be expected. The highest forecast is 7.6% growth from the Cowan LRA model. The Cowan model is based on historical trends and does not take into account current events such as COVID-19. Omdia expects 2.5% growth. Gartner expects a decline of only 0.9%. McKinsey calls for a decline of 5% to 15% (with a -10% midpoint). IBS is the most pessimistic at an 11.7% decline. IC Insights and IDC each project a decline of about 4%. Our latest forecast from Semiconductor Intelligence is a 6% decline in 2020.

The memory market remains the one bright spot in the semiconductor market in 2020. Gartner expects memory to grow 14%. Gartner forecast a 6% decline in semiconductors excluding memory, compared to a 0.9% decline for total semiconductors. Omdia also see memory driving grow, with its 2.5% growth forecast for semiconductors dropping to a 5% decline excluding memory.

A precedent exists for a V-shaped recovery for the semiconductor market. At the beginning of the great recession in 2008, the semiconductor market dropped sharply with a 24% quarter-to-quarter decline in 4Q 2008 and a 16% decline in 1Q 2009. The severe economic contraction led electronics manufacturers to cut inventories in preparation for a potential severe drop in demand. As it turned out, electronics markets did not see a major impact from the recession. PC units grew 5% in 2009. Mobile phone units dropped 3% in 2009, but the newly emerging smartphone market was a booming. The semiconductor market had a steep recovery, with 20% quarter-to-quarter growth in 2Q 2009 and 3Q 2009. By 4Q 2009 the market was basically back to pre-recession levels.

Our Semiconductor Intelligence forecast is more of a U-shape than a V-shape. A sharp drop in 2Q 2020 should be followed by a relatively stagnant market in 3Q and 4Q 2020. Growth is expected to pick up in the first half of 2021. We expect the semiconductor market will grow 10% to 15% in 2021.

Also Read:

COVID-19 and Semiconductors

Semiconductor Recovery in 2020?

CES 2020: still no flying cars