SemiWiki – Page 384 – The Open Forum for Semiconductor Professionals

May 20, 2020January 19, 2021

Collaboration Flow for Moore’s Law versus More than Moore

Collaboration Flow for Moore’s Law versus More than Moore
by Herb Reiter on 05-20-2020 at 10:00 am
Categories: EDA, Foundries, IP, Semiconductor Services
2 Comments

The current Coronavirus crisis is inflicting a lot of pain on people, companies, and governments. I hope I am not getting in trouble with my reasoning, but if you look closely, there are also some “positives” to the Covid-19 crisis.

– It is stress-testing our infrastructure and telling us where we need to improve – as country, states, communities, companies, and individuals – to benefit long-term.

– Empty shelves and/or purchase quantity limits at grocery stores show us the importance of a solid supply chain.

– Extremely high demand for laptops, iPads, video cameras, and other essentials for working remotely, tell us that High-Tech is a great industry to work for and that we have a lot of opportunities for growth – if we get the pricing right.

Allow me to pick up on “getting the pricing right” and outline some ideas how to streamline the High-Tech supply chain, to further lower the cost of electronic products, make it easier to set up home offices and grow our revenues and profits.

From 1980 until ’96 I worked in the manufacturing part of the semiconductor supply chain, at two big IC vendors. Since 1997 I am in the Electronic Design Automation (EDA) portion, focused on encouraging the use of EDA tools to make semiconductor manufacturing more efficient and more cost-effective, by broadening the collaboration between EDA and manufacturing experts.

EDA and wafer foundry experts have made remarkable progress in the last forty years. For example: in 1980 I sold my first ASIC at two cents per gate; today two cents buy you at least one Million gates. Excellent collaboration between material suppliers, equipment vendors, wafer foundries as well as EDA, IP and IC design experts made such progress possible.

Figure 1 shows a significantly simplified Collaboration Flow between the essential parties. They have enabled in the last four decades enormous IC complexity increases, broadened the range of functionalities and, at the same time, reduced cost per function by six orders of magnitudes.

Figure 1 Collaboration with Foundry

During the 2008 financial crisis, rumors about the end of Moore’s Law and the need for More than Moore started. I took this as an opportunity to change my focus from the traditional single-die SoC technology to multi-die ICs (2.5/3D-ICs). In these new technologies the package adds a lot of value to the complete solution. Until that time, I was used to being part of the broad and in-depth cooperation between EDA vendors and wafer foundries, developing Process Design Kits (PDKs) and Reference Design Flows. That’s the reason why I was surprised that IC assembly/test houses (a.k.a. OSATs), at that time, were not as proactive as wafer foundries. They had no design kits, nor reference flows, and the excellent engineers at the OSATs had to spend a lot of manual efforts, to meet their customers’ IC packaging and cost requirements.

Thanks to industry organizations, like the Global Semiconductor Alliance (GSA), SEMATEC, the Silicon Integration Initiative (Si2), the Electronic System Design Alliance (ESDA), MEPTEC and SEMI, who gave me “a soap-box” to better highlight the industry’s pressure for more automation between IC designers and OSATs, several OSATs have developed since, in cooperation with their EDA partners, Assembly Design Kits (ADKs) and Design Reference Flows for packages. Figure 2 shows a significantly simplified Collaboration Flow between the essential parties, to reduce package development time and engineering cost. Please, DO NOT plan on six magnitudes in package unit cost reduction. To achieve this target, IC packages would need to be shrunk so much, that nobody could see or use them anymore.

Figure 2 Collaboration with OSAT

Bottom Line: Assembly Design Kits and Design Reference Flows encourage the use of off-the-shelf or “pre-customized” packages. Yes, they do limit IC designers’ flexibility somewhat, but the significant savings in development time and engineering cost, as well as lower manufacturing cost will reward IC Vendors and OSATs royally for streamlining/automating their collaboration. Best of all, ADKs and Reference Flows make IC package design and manufacturing very scalable!!!

May 20, 2020September 30, 2020

eFPGA – What’s Available Now, What’s Coming and What’s Possible!

eFPGA – What’s Available Now, What’s Coming and What’s Possible!
by Daniel Nenni on 05-20-2020 at 6:00 am
Categories: eFPGA, Flex Logix, IP
7 Comments

eFPGA is now widely available, has been used in dozens of chips, is being designed into dozens more and it has an increasing list of benefits for a range of applications. Embedded FPGA, or eFPGA, enables your SoC to have flexibility in critical areas where algorithm, protocol or market needs are changing. FPGAs can also accelerate many workloads faster than processors. For example, Microsoft Azure uses one FPGA accelerator for every 2 Intel Xeons. Flex Logix provides eFPGA cores which have density and performance similar to leading FPGAs in the same process node. The EFLEX eFPGA is silicon proven in 40nm down to 12nm with 7nm in process.

WEBINAR: eFPGA What’s Available Now, What’s Coming & What’s Possible!

In this webinar Andy Jaros talks about the emergence of eFPGA over the last five years and the success of Flex Logix amongst multiple market segments. Here is a quick update from their website:

“We are solidly funded and backed by strong Venture Capitalists Lux and Eclipse. We have proven our eFPGA technology in 180nm, 40nm, 28/22nm, 16nm and 12nm with TSMC and GlobalFoundries. There are more than 10 working SoCs with our technology and >>10 more in fab/design. Our customers are very well funded organizations and companies and our technology is strategically critical to them. Our cash in the bank and our backlog/commitments mean that we do not need to raise cash in 2020 and we can fund our AI Inference chip development and production ramp from cash flow. Our AI chip, InferX X1, benchmarks with superior price/performance on real-world neural network models customers have given us. As X1 ramps production our financial situation will be even stronger.”

Andy Jaros is one of my trusted few. He is the VP of Sales and Solutions Architecture at Flex Logix. Andy has more than 30 years of semiconductor experience most of which involves IP, most notably ARC, Virage Logic, and Synopsys. I was at Virage when we acquired ARC and that is where I first met Andy, who is also a neighbor of mine. He continued on with Synopsys after they acquired Virage and then moved to Flex Logix more than 4 years ago. At that time eFPGA was just another acronym. Today, Flex Logix is the leading provider of embedded FPGA hard IP and software. Flex Logix is also launching Inference Acceleration chips for Edge Applications so they are not just an IP company.

Flex Logix came to SemiWiki four years ago and we have now published 40 blogs with them that have earned more than 250,000 views. Excellent content gets excellent views, absolutely.

The webinar is coming up so register now:

WEBINAR: eFPGA What’s Available Now, What’s Coming & What’s Possible!

Here are the questions I have for Andy. If you have others let me know:

What is the area penalty for using an eFPGA?

How does the eFPGA get programmed and by who?

What specific design considerations do you need to make for eFPGA use?

May 19, 2020April 26, 2022

Cost Analysis of the Proposed TSMC US Fab

Cost Analysis of the Proposed TSMC US Fab
by Scotten Jones on 05-19-2020 at 10:00 am
Categories: Semiconductor Services, TechInsights, TSMC
29 Comments

On May 15^th TSMC “announced its intention to build and operate an advanced semiconductor fab in the United States with the mutual understanding and commitment to support from the U.S. federal government and the State of Arizona.”

The fab will run TSMC’s 5nm technology and have a capacity of 20,000 wafers per month (wpm). Construction is planned to start in 2021 and production is targeted for 2024. Total spending on the project including capital expenditure will be $12 billion dollars between 2021 and 2029.

This announcement is undoubtedly the result of intense pressure on TSMC by the US government and it is also coming out today that TSMC will stop taking orders from Huawei also under pressure from the US.

What does this fab announcement mean?

This announcement is in my opinion soft, “Intention to build”, “construction planned to start”, “production targeted”. The project is based on a “mutual understanding and commitment to support from the U.S. federal government and the State of Arizona”, What happens if Donald Trump is voted out in November or just changes his mind? I could easily see this project never materializing due to changes in the US political situation or lack of follow-through from TSMC who is likely not excited about it to begin with.

My company IC Knowledge LLC is the world leader of cost and price modeling of semiconductors and MEMS. I thought it would be interesting to use our Strategic Cost and Price Model to make some calculations around this fab.

TSMC operates four major 300mm manufacturing sites in Taiwan and one in China. The four sites in Taiwan are all GigagFab sites, Fab 12, Fab 14, Fab 15 and Fab 18 are each made up of 6 or 7 wafers fabs sharing central facility plants. This Gigafab approach is believed to reduce construction costs by about 25% versus building a single stand-alone fab. The china fab location is smaller with 2 fabs at one location but the fab was equipped with used equipment transferred from fabs in Taiwan because the fab is trailing edge. If TSMC really builds a single US fab running 20,000 wpm the resulting cost to produce a wafer will be roughly 1.3% higher than for a GigaFab location due to higher construction costs. I believe it is unlikely the site will be equipped with used equipment transferred from Taiwan. The cost to build and equip the fab for 20,000 wpm should be approximately $5.4 billion dollars.

Locating a fab in the US versus Taiwan will result in the fab incurring US labor and utility costs, this will add approximately 3.4% to the wafer manufacturing cost.

The capacity of the fab is also smaller than a “typical” fab at advanced nodes, the three 5nm fabs TSMC is operating or planning for Taiwan are all 30,000 wpm. A 20,000 wpm fab will have an approximately 3.8% increase in costs versus a 30,000 wpm fab under the same conditions.

In total, wafers produced at the TSMC Arizona fab will be approximately 7% more expensive to manufacturer than a wafer made in Fab 18 in Taiwan. This does not account for the impact of taxes that are likely to be higher in the US than in Taiwan.

In the announcement TSMC has said the total spending on the project between 2021 and 2029 would be $12 billion dollars. That leaves money for a future expansion or conversion to 3nm. That would be almost enough money to add a second 20,000 wpm fab running 3nm as one possible example.

In summary the “announced” fab would likely be TSMC’s highest cost production site. It will be interesting to see if the fab materializes.

Also Read:

Can TSMC Maintain Their Process Technology Lead

SPIE 2020 – ASML EUV and Inspection Update

SPIE 2020 – Applied Materials Material-Enabled Patterning

May 19, 2020January 12, 2021

Is Mutation Testing Worth the Effort? Innovation in Verification

Is Mutation Testing Worth the Effort? Innovation in Verification
by Bernard Murphy on 05-19-2020 at 6:00 am
Categories: Cadence, EDA
5 Comments

Mutation testing is an intriguing idea, but is it useful? Paul Cunningham (GM of Verification at Cadence), Jim Hogan and I continue our series on novel research ideas, here looking at a paper examining the pros and cons of this topic. Feel free to comment if you agree or disagree.

The Innovation

This month’s pick is Which Software Faults Are Tests Not Detecting? The paper was presented at the 2020 Evaluation and Assessment in Software Engineering conference. The authors are all from Lancaster University in the UK.

The contribution in this paper is analysis of testing efficiency in software, to find methods to improve the ability of tests to uncover more bugs. The authors measure efficiency through a combination of code coverage and mutation analyses. In mutation testing functional errors are inserted in the code, testing is re-run and test efficiency is determined by ability to detect the mutation. They apply their analysis to 10 open-source systems with associated unit tests, using a tool to automatically insert faults. From this they analyze efficiency of the tests by fault type.

They report that in 6 of the systems, less than 50% of the injected faults are detected and some fault types are detected more frequently than others, particularly conditional boundary checks. They also find that the lowest performing tests are 10X less efficient in detecting boundary faults.

The authors also discuss challenges in mutation testing. One study finds that most post-release faults are complex and can only be fixed through modifications in several locations. Attempting to model these through mutation would explode rapidly. Also, a study at Google confirms that even simple mutation testing is very expensive. Many mutants are unproductive, being either redundant or equivalent, yet are not easily weeded out.

Paul

This is something we’re looking at closely as a natural area of interest in our metric driven verification (MDV) strategy. We’re always interested in ways to help improve test effectiveness; this paper adds to our understanding.

Testing mutated code is computationally expensive, whether it’s software or hardware, since you have to run all your tests not only on the original code but also on each mutated version. In hardware verification, testing the non-mutated design is already swamping verification resources. If we are going to do mutation testing in hardware, we need to focus on high ROI mutations. A second concern is that mutation testing exposes limitations in tests, not bugs in the design. Which is still valuable but not a first-order concern, making it a tougher sell for schedule-constrained projects.

Nevertheless, selective use of high ROI mutation coverage could still be helpful in hardware, especially for modules where there is no good functional coverage model available. The paper cites boundary condition mutation, for example, mutating “<=” with “<” as more likely to find useful gaps in tests than mutating “+” with “-“. Buffer overflow security attacks are given as a good example where boundary condition mutation can catch gaps in test suites. This example applies equally to both software and hardware test.

Very thought-provoking.

Jim

The observation I want to make here, as an investor is that I have seen a decline in research in functional verification at the RTL level, at least judging by the number of papers we see. Not application-level stuff, how to better use the tools we’ve already got, that’s common. I’m talking about original research, from universities or outfits like Google.

This isn’t because all the problems are solved – they definitely aren’t. I think it’s more for universities because grants are directed to problems in other areas, and in the hyperscalars because software is their biggest driver for innovation. What then should we do in functional verification for hardware? Learn from research in software verification! The two domains are very closely related, not identical but the overlap is significant. I want to see more of these software parallels.

On this topic specifically, I want to better understand the associated costs. That’s a huge factor in ROI; the “R” will have to be equally impressive.

Security seems like a good application for mutation testing. Here there may be more willingness to accept the added overhead, also the recently released Mitre list of common weaknesses in hardware should provide inspiration for more security-related high-value mutations beyond boundary conditions.

To see the previous blog click HERE. You can see the next blog HERE.

May 18, 2020August 2, 2020

TSMC stops doing business with Huawei!

TSMC stops doing business with Huawei!
by Robert Maire on 05-18-2020 at 9:30 am
Categories: China, Semiconductor Advisors, Semiconductor Services
15 Comments

Hours after agreeing to build a fab in US TSMC will stop selling to Huawei- Repercussions will reverberate through all tech: Semis, semi equip, chip customers, all collateral damage.

It has been reported by Nikkei and other sources that TSMC has stopped taking orders from Huawei in order to comply with US export controls.

HUAWEI CRACKDOWN

This comes literally hours after TSMC agreed to build a fab in the US. While this does not impact chips in the production process or already ordered it does stop new business . The Commerce initiative sets a hard deadline of September 14th to cut off business. This suggests that Huawei likely has at least 3-4 months or so before the impact will start to limit business. They likely have been stockpiling chips in anticipation of such a move.

A “virtual” death sentence for Huawei-
Much like we saw Jinhua die almost over night after the supply of US technology was stopped, it is clear that Huawei will no longer be competitive in the market against either Apple or Samsung in mobile phones and severely hampered in their network equipment side.

While Huawei will obviously try to shift chip production to Chinese suppliers and SMIC to fabricate the chips, SMIC is hindered in that it is several generations behind TSMC and its supply of EUV tools from ASML has also been cut off by the US.

It will take a while for the impact to be felt as Huawei has stocked up and chips are still in process but in a few months time those supplies will dry up and leading edge product will become unavailable.

We don’t think that this is a negotiating ploy by the current administration…it feels too real this time. Even though there is time to negotiate yet another deal, we don’t see the administration relenting before November as they want to be seen as hard on China both in retribution for Covid and less than successful trade deals.

Every US chip company will get hurt
Every US semiconductor Company from Intel and Qualcomm down to the smallest analog maker will be negatively impacted as China will go so far out of its way to avoid “buying American”. Without doubt they will use inferior, trailing technology from inside China or other sources rather than rely on unreliable US made components that could be shut off at any moment.

China can’t turn to Samsung
Even though Samsung’s foundry division would love to get Huawei’s business, it isn’t going to happen. Number one, Samsung is obviously a competitor to Huawei in the handset business and number two, Samsung would never risk its semiconductor production to US sanctions, which is its life blood and the vast majority of its profitability.

This is of course aside from the fact that South Korea is very reliant on the US versus North Korea

US chip equipment sales to China will be cut
We were amazed that both KLA and AMAT blew off the embargo risk to China as if it was nothing by saying that they will just ship equipment from another country…no big deal…we can easily get around the restrictions. It was even more amazing that allegedly intelligent analysts on the call didn’t question this and just accepted it.

While shipping US know how, technology and IP from another country where the last screw is installed in the equipment may comply with the letter of the law as it stands today (which is unclear at best) its obviously in clear, blatant opposition of the spirit of the law which is to deny US technology to companies that supply Huawei (read that as any China based chip company).

This loophole will be closed and may already be closed if you read documents from the commerce department.

Commerce Addresses Huawei’s Efforts to Undermine Entity List, Restricts Products Designed and Produced with U.S. Technologies

Federal Register Language

Semiconductor equipment sold by AMAT, KLA & Lam, among others, even if manufactured, in whole or in part, outside the US , still clearly contain “US software & technology” which is the key target of restrictions by the US commerce department. The target of the restrictions is not where its made but what it contains…..

This means that semiconductor equipment companies entirety of business with China, ranging from 25% to 50% of revenues in some cases is at risk. This also includes sales to multi nationals who have a fab in China (including Intel, Samsung and others) not just indigenous fabs.

TSMC was forced to choose sides and picked the US
Like two primary school dodge ball teams choosing players for their side going after the best player available, TSMC was stuck in the middle and didn’t want to upset either the US or China. The US stepped up the pressure by threatening to cut off TSMC’s “oxygen” in the form of semiconductor equipment and TSMC quickly capitulated by not only announcing a fab in the US (even though its a token, show fab) but much more importantly blowing off their second biggest customer after Apple…Huawei. All of this knowing full well that this would turn into a major political football with China being a short sail away from Taiwan.

Its not like TSMC (or Taiwan for that matter) had much choice. Either embrace the US fully or just surrender today to China and hand over the keys to the island and the fabs to the “barbarians at the gate”.

Others will be forced to choose sides as well. The US dodgeball team already has the Dutch and sooner or later Japan and Korea chip companies will have to choose sides. Israel is already there. The US has already been playing a “warm up game” in pressuring foreign countries on Huawei made networking gear.

The stocks and the fallout—–both ugly
Chip companies have a huge amount of business in China as China makes 70% of the worlds electronics goods. Apple is a top target, Boeing, even Tesla could be targeted.

Semiconductor equipment companies will lose business not shipped by Sept 14th and more in the long term as China steps up its efforts to be independent.

The impact won’t be felt in the June quarter, nor the September quarter but the December quarter will be off a cliff.

In a perverse way, near term business will actually be up significantly as Chinese companies rush to get any chips and equipment into the country before the Sept 14th deadline. This means June and September could be better for Chinese business than expected.

Long term damage has already been done. Lots of losers….
Unfortunately, even if the US and China could patch things up by some miracle, which isn’t happening any time soon, the long term damage has already been done.

China will rightfully triple down on becoming chip independent from the US and US companies will lose more business than ever.

Right now US/China tensions are very high but we are the two largest trading partners in the world and still do billions in business per day.

This will trickle down through Taiwan, the South China sea, Europe, Africa and beyond.

The global economy needs this like another hole in its head after getting whacked by Covid.

This increases our view that the fall is going to be very, very ugly for chips due to both the trickle down of the economic slowdown coupled with China trade problems….the “double, super duper, whammy”

Semiconductor Advisors

Semiconductor Advisors on SemiWiki

May 18, 2020October 3, 2020

HCL Offers Tightly Integrated Design Management Solution for Virtuoso

HCL Offers Tightly Integrated Design Management Solution for Virtuoso
by Tom Simon on 05-18-2020 at 6:00 am
Categories: EDA, HCL Software

The road to a truly usable design management solution for electronic design has been a long and twisty one. Initially just handling EDA tool data was a struggle, let alone addressing mutli-user and multi-site needs. Of course, all along every EDA tool development company was internally using software revision control, which worked fine for source code, but was not efficient or practical for large binary files produced by layout tools, etc. The first generation of usable design management tools came as ad hoc vendor specific solutions that were part of the EDA frameworks. They suffered from lack of scalability and being vertical silos for each vendor. However, they did usually offer the advantage that they understood the library, cell, file schema of the underlying designs.

To break the log jam, it would take software companies that specialized in revision control, project management and more. Rational Software was an early leader in revision control for software development and other types of design management. Their innovative solutions were used outside of EDA for a long time. Because of their high performance and scalability, they made inroads into flows based on HDLs and firmware. However, a solid solution for analog and custom design waited until about 8 years ago when they developed a Cadence integration.

Along the way the ClearCase software moved between several different companies. Most recently it was owned by IBM. In 2016, seeking to accelerate development, IBM announced a partnership transferring development to HCL Technologies. This has ensured the proper level of resources and focus for the ClearCase offerings.

It’s easy to see why Cadence users would like the Flexiem design management solution from HCL based on ClearCase. It takes only seconds for a user to create a workspace where they can start working on and accessing everything needed for a design. Even though the design data may reside on multiple servers in local or remote locations, the Multiple Version File System (MVFS) creates a virtual file system where every file is immediately referenceable. Unmanaged files can easily be created and then checked in to make them managed.

Most importantly, Flexiem offers tight integration within the Cadence environment. Design views can be checked in and out within the Library Manager. The Flexiem integration with Cadence understands the design hierarchy and even is aware of schematic level changes between versions. With these features it is easy to check in or out complete design hierarchies in one step.

Because ClearCase is used widely within many enterprises, using it for design management harmonizes well with existing infrastructure. Flexiem also offers a rich and sophisticated access control system which is vitally important for managing who can see and/or make changes to design data. One benefit of this is the ability to protect and track internal and external IP. As hinted to above, the Versioned Object Bases (VOBs) for a design can be local, remote or distributed in a manner that is transparent to the user. Similarly, users can work in teams across geographic boundaries.

The overall level of capabilities that can be provided by a system as mature as the ClearCase based Flexiem would simply be impossible for an EDA vendor to develop. Flexiem is also tool vendor agnostic, so it can fit into flows with a wide variety of tools.

HCL has produced a video that will provide an overview of Flexiem as used for EDA design management. If you want more information, this video would be a good starting off point. Having worked with many design management systems over my career, I can say that the offering from HCL hits the sweet spot in term of performance, usability and maturity.

May 17, 2020May 17, 2020

10 Areas of Change in Cybersecurity for 2020

10 Areas of Change in Cybersecurity for 2020
by Matthew Rosenquist on 05-17-2020 at 10:00 am
Categories: Security

Cybersecurity in 2020 will be evolutionary but not revolutionary. Although there is always change and churn, much of the foundational drivers remain relatively stable. Attacks in the next 12 months are likely to persist in ways already known but taking it up-a-notch and that will lead to a steady escalation between attackers and defenders. The growth of devices, users, and data continue to expand the playing field while the weaknesses of people’s behaviors continue to contribute to the greatest risk factors for compromises.

Here are some of the key areas to keep an eye on.

2020 Cybersecurity Predictions

Internet-of-Things (IoT): IoT continues to expand with insecure devices, services, and interfaces. Another 4 billion IoT devices will come online in 2020. Devices being hacked and insecure data being compromised are the two primary threats. Some progress will be made with the retirement of default or no passwords, but IoT devices will still be far from secure. At the same time, such devices will be called upon to handle even more sensitive data. Overall, the risks increase as devices become more autonomous and are employed in sensitive industries like healthcare, critical infrastructure, transportation, security, and remote-work applications.
Cybersecurity Workforce: The demand for cybersecurity professionals continues to rise and outpace the available talent pool. By the end of 2020, there will likely be over 3 million unfilled positions. Such a global shortage leaves a dangerous range of organizations under-resourced to protect assets, services, data, and people. Leadership and technical roles will be in the highest demand. Ironically, entry-level placement will be difficult for those without experience. Frustration will fester for many entering into the field. The training gap remains for 2020 and beyond, but academic institutions will continue to move, albeit slowly, to close the deficiencies in preparing the next generation of cybersecurity professionals
Critical Infrastructure (CI): The war targeting critical infrastructure will heat up while remaining largely stealthy. Nation-States will jockey for access in the systems of potential adversaries. Defenders will actively pursue detection and eviction, but never achieve a high level of confidence. It is a chess game where the winner retains a foothold that could be used in the future as part of a devastating attack, to send political messages, or fuel disruption. On a positive note, no major critical infrastructure attacks will occur in 2020, at least on purpose. Accidents do sometimes happen at this level of gamesmanship. Vital sectors including government, communications, transportation, logistics, energy, national industries, and even healthcare are all potential targets for compromise. This is part of the long-game that countries play against one another.
Cybercrime: The number of cybercriminals and attacks grows significantly, victimizing more people and incurring losses that may approach $6 trillion by the end of the year. At the top, the organized and funded crews will continue to expand and orchestrate top-tier attacks as well as massive fraud at an ever-growing scale. At the bottom of the cybercrime hierarchy pyramid, swells of novice criminals will join the ranks to help with basic labor-intensive duties. Financial hardship, desperation, and a lack of other options will draw new internet users from economically struggling geographies to venture into cybercrime. They are lured into activities such as botnet/malware distribution, money and reshipping mule duties, ransomware-as-a-service (RaaS) victim on-boarding, social engineering data harvesting, human authentication verification, amplification of investment scams, and propagation of retail fraud to make money. As a result, the global online community will suffer from an increase of ransomware, denial-of-service, online-harassment, data breaches, financial fraud schemes, and cryptojacking. The severity will drive up the overall losses due to cybercrime. The elite digital syndicates will target specific organizations for big scores with Business Email Compromises (BEC), financial transaction tampering, and data accessibility ransoms in the millions. The largest single attacks of 2020 will likely reach into the hundreds of millions in losses.
Passwords/Authentication: Multi-Factor Authentication (MFA) and Two-Factor Authentication (2FA) will remain largely ignored, regardless of the massive fleecing of accounts. Throughout the year, consumers will feel much more pain from highly automated credential-stuffing capabilities that are coupled with exploitation features for account hacking, extortion demands, and theft. Small and medium businesses (SMB) will feel the greatest pain and will struggle to find a balance between the risks, costs, and usability friction.
Privacy: Privacy compliance will be expensive, convoluted, and political. Expectations of customers will increase for companies to keep their data private. Credit monitoring will not be enough to appease the masses. Regulatory authorities around the globe will begin greater prosecution of offenders. The news will highlight more lawsuits, massive regulatory penalties, greater customer abandonment, and executives losing their jobs because of poor choices in protecting private data or not satisfying regulations.
Artificial Intelligence (AI): AI attacks and defenses will rise to a new level. Attacks will be more customized and scale to target large pools of potential victims. Defenses will lag, but also begin finding optimal ways to detect and block these types of attacks. Implementation of AI tools by the attackers and defenders is still in the early phases of what will be a very long and drawn out arms race.
Malware: Vulnerability discovery, exploit creation, and development of malicious software will accelerate. It will also expand from the server, PC, and smartphone domains to include many more types of devices and services. Technical exploitation techniques get more sophisticated, but social engineering does not. It simply doesn’t need to. Humans continue to be the weakest link in the ecosystem and remain the primary means for practical compromises.
Zero-Trust: “Zero-Trust” will remain a marketing buzzword for most of the year. Basic standards and more narrow accepted concepts begin to emerge around Zero-Trust security. By the end of 2020, there will still not be a complete consensus, standards, or frameworks. As leaders emerge, customers will begin to fall into certain camps. Results will continue to vary for this premium capability. Expect various re-branding and renaming to ensue as the term begins to become stale and loses favor with marketing types because of a lack of competitive differentiation.
5G cybersecurity risks: The security fears of 5G reached its pinnacle in 2019. A lot of hype but real risks won’t actually manifest in 2020. Yes, 5G allows for greater speed, lower latency, and more connection density but that plays for both sides. Risk organizations realize it is just the natural evolution of the battlefield, not a super-weapon. People will briefly wonder what all the fuss was about, as they enjoy a better experience. Security pundits will shift gears to focus on the next sexy potential emerging threat that could boost their budgets. Pity they aren’t focusing on the human behavioral weaknesses that represent a much greater problem.

The aggregation of these factors will contribute to a thriving cybercrime industry that will show no mercy in 2020. Tools for both attackers and defenders get better. The size and complexity of our digital world will increase significantly, creating scalability issues for security while opening new opportunities for threats.

The biggest overall concern for 2020 will be that significantly more data will be in peril. Vast amounts of data will be created and potentially exposed from significantly increasing numbers of devices, services, and users. Nearly 400 thousand new internet citizens will join the connected digital world, with the largest percentage from economically struggling countries. Businesses and governments will continue to gather more information than needed and aggregate it in ways that consumers did not expect. Security will remain weak, with protections lacking for data in-use, in-transit, and at rest.

Although 2020 predictions may sound extreme, this is the normal progression for cybersecurity. It should draw a mild yawn from security professionals who are familiar with maneuvering these troubled waters every day. The best of them will remain vigilant and keep continued pressure on intersecting the tactics, techniques, and processes of attackers to drive increasing demand for better and more coordinated cybersecurity throughout the year.

May 17, 2020May 18, 2020

COVID-19: A Pandemic Made for Tesla

COVID-19: A Pandemic Made for Tesla
by Roger C. Lanctot on 05-17-2020 at 6:00 am
Categories: Automotive
2 Comments

With Tesla Motors’ CEO Elon Musk spewing accusations of civil rights violations and fascism in the face of restrictions forcing him to keep his Fremont, California factory closed it is tempting to assume that Tesla is suffering through the shutdown with the rest of us. Don’t kid yourself. The COVID-19 pandemic is a crisis tailor-made for Tesla and one upon which Musk is even now capitalizing.

Musk’s Tesla is perfectly positioned for this pandemic. While parking lots are filling up with unsold cars and dealers are champing at the bit to be allowed to sell cars, Tesla Motors continues to deliver cars directly to consumers. Musk even went so far on the earnings call as to tout his progress toward a touchless vehicle purchasing proposition allowing a vehicle acquisition to occur within five minutes from a mobile phone app.

Tesla earnings recording: https://ir.tesla.com/events-and-presentations

Cars.com reports that dealers across the U.S. are struggling with 50 different state-level regulatory approaches to stay-at-home orders with some allowing vehicle repairs but no sales, others allowing only online sales, and many actually allowing vehicle sales from retail stores. There’s just one problem, consumer surveys show that potential buyers by-and-large don’t want to visit dealerships at this time.

Cars.com reporting: https://www.cars.com/articles/coronavirus-and-cars-can-i-buy-a-car-or-have-one-repaired-in-my-state-420549/

For their part, dealers have been scrambling to enable online sales – wrangling with local restrictions and restrictive franchise laws intended to protect traditional automobile retailing from online sales that have now become a barrier to that very thing.

While dealers and governors and regulators wrangle, Musk is laughing all the way to the bank. On last week’s earnings call he joked that buying a car these days is like a visit to the dentist – only worse.

SOURCE: Images of the jam-packed parking lots at the Port of Los Angeles on April 24th, with the Jupiter Spirit waiting with its cargo of cars in the harbor. Satellite images courtesy of MAXAR.

From one of his multiple homes in Los Angeles one can imagine Musk LOL-ing at the Jupiter Spirit, a container vessel loaded with 2,000 Nissans, idled in the harbor for weeks waiting to offload its cargo while personnel onshore scrambled to make room for the incoming vehicles. Needless to say, Tesla Motors doesn’t have those kinds of troubles. Those are the kinds of troubles reserved for the makers of gas-fueled automobiles sold by instantly irrelevant dealers.

Musk may put on a good show for the analysts and stockholders over California limiting his production plans, competitors may even cluck their schadenfreude-ish tongues his way, but it is clear that Tesla’s moment has arrived. An electric powertrain for a vehicle directly delivered to customers is a business model from the future with which today’s automobile industry is unable to compete.

Not content to humiliate competing car makers and disintermediate an entire distribution channel with millions of workers, Musk says he is adding operating-room-grade in-vehicle air filtration to his cars. (Ford Motor Company manufactured personal protective equipment and General Motors made ventilators to combat COVID-19. Tesla created its own ventilator from Model S and Model 3 parts – but never delivered.)

While the legacy auto industry spins its wheels and struggles to drop the clutch on massive structural impediments to its own progress, Tesla is waiting for the flag to drop on the final stage of its industry take over. Forecasters are talking about post-COVID-19 declines of 20%-25% in vehicle output globally, while Tesla is notching its growth rate expectations down to 40% from 50%.

Tesla can restart at the flip of a switch. The competition needs a week to ramp up supplier factories before revving production back up. But that revved up production will be shipping into a massive back-up of unsold vehicles – including cars returned from ailing rental car companies.

To make matters worse, Tesla will instantly begin shipping cars directly to consumers while dealers struggle to simultaneously reassure customers that it’s okay to visit newly opened showrooms while offering online sales, for many of them, for the first time.

Meanwhile, the pandemic impasse gives Musk yet another soapbox to proclaim his defense of the common man against the ravages of government regulators and the legacy auto industry (from this week’s earnings call):

“So, the extension of the shelter-in-place or, frankly, I would call it, forcibly imprisoning people in their homes against all their constitutional rights…Tesla will weather the storm (but) there are many small companies that will not. And … everything people have worked for their whole life is going to get — is being destroyed in real time. And we’re going to have many suppliers — or have many suppliers that are having super hard times.

“I think the people are going to be very angry about this … They should be allowed to stay in their house, and they should not be compelled to leave. But to say that they cannot leave their house, and they will be arrested if they do, this is fascist. This is not democratic. This is not freedom. Give people back their goddamn freedom.”

Needless to say, no competing auto maker CEO is capable of speaking this freely. It’s pretty potent yet apolitical stuff. Just raw meat for Tesla fans, Tesla owners, and those that want to own a Tesla. One can almost imagine the masses in driving gloves and bearing pitchforks and torches marching on the municipal offices in Fremont shouting: “Free Elon!”

It is high noon in the automotive industry. COVID-19 has brought the future to the industry’s doorstep. It’s now or never for every legacy auto maker and dealer to step up their game, step up their product, step up their incentives, step up their outreach, step up their service, and get in the game. Nothing will ever be the same. We are all now on COVID-19 time.

May 15, 2020August 27, 2020

WEBINAR: Moving UVM Verification Up To The Next Level

WEBINAR: Moving UVM Verification Up To The Next Level
by Daniel Nenni on 05-15-2020 at 9:00 am
Categories: EDA, Events, Siemens EDA
2 Comments

Tom Fitzpatrick, a Strategic Verification Architect at Mentor, a Siemens Business, has worked on IEEE and Accellera standards like Verilog 1364, System Verilog 1800, UVM 1800.2 and is Vice Chair of the Portable Stimulus working group, so when I heard that he was doing a webinar on how PSS can be used to create better stimulus for a UVM environment, I previewed it right away to improve my understanding. The webinar helped me better understand the important and powerful relationship between PSS and UVM and also included a few details about how Mentor is making PSS technology available “under the covers” for UVM users in their inFact CX product. For those interested, the webinar will be hosted on Tuesday, May 26^th from 10am-11am PDT and you can register here. I’ve included what I believe to be some stand-out points below.

A biannual verification survey conducted by Wilson Research Group has listed the biggest verification challenge for both ASIC and FPGA users as the ability to create sufficient tests to verify the design and achieve coverage closure.

The Portable Test and Stimulus Standard (PSS) provides a common verification language across IP blocks, subsystem and full system. Even as your SoC goes through multiple generations, you can reuse verification intent. Finally, you can use a single specification across simulation, emulation and FPGA prototyping, saving you much time as compared to separate approaches.

In the specification of PSS it states, “The goal is to allow stimulus and tests, including coverage and results checking, to be specified at a high level of abstraction, suitable for tools to interpret and create scenarios and generate implementation in a variety of languages and tool environments, with consistent behavior across multiple implementations.”

So, UVM is just one possible target environment for Portable Stimulus.

A typical UVM verification flow starts with a sequence item and set of constraints, then it’s run through random simulation, sending transactions through the agent to the DUT, covergroups measure coverage metrics, but then we often realize that our coverage goals are not met. At this point, we can write new constraints to target additional coverage, but ultimately we need to write directed tests to reach the last 5-10% of coverage.

This is the result of constrained-random simulation treating the coverage specification as passive. In a typical constrained-random testbench, you are defining your critical states (green circles), and then constrained random tests hit those states in unpredictable ways. On the downside, constrained random will often repeat states or entirely miss coverage points. With this passive coverage approach we can still see lots of uncovered states, including states that may indicate a bug.

Instead of relying on procedural tests and hoping you’ll hit your coverage goals, PSS is a declarative language that lets you define scenarios at an abstract level and lets your tool, such as Questa inFact, generate different target-specific implementations of the abstract scenarios in either SystemVerilog (including UVM) or C. Because the PSS scenarios are fully declarative, the tools can analyze the scenarios and generate tests that actively target your coverage goals.

Thus, a tool like Questa inFact can generate the minimum number of tests required to reach your coverage, and then generate all other legal scenarios that will fully exercise all other states, including the one with the bug.

When all is said and done, the PSS description is transformed into a UVM virtual sequence that calls lower-level UVM sequences in the right order to implement the abstract scenario you described.

You can then use the UVM factory to simply swap in the PSS-generated sequences into your existing UVM environment without having to change any of your UVM code.

Summary
PSS allows you to look at verification from a higher level, because it’s declarative. This does require a change in thinking for most UVM users. Mentor’s Questa inFact automates a lot of the analysis to hide most of the PSS details and extracts the important details from your existing UVM code to build a coverage-targeted test for you. As you can see below, using PSS with a tool like Questa inFact (green line) when compared to constrained-random (red), lets you reach your test coverage goals much more efficiently, giving you more time to explore additional scenarios outside of your coverage scope, with the promise of 2-3X improvement in regression efficiency.

Plan to signup and attend this webinar online on May 26th, which also includes a Q&A.

May 15, 2020August 27, 2020

WEBINAR: Transitioning from Live to Virtual Events

WEBINAR: Transitioning from Live to Virtual Events
by Daniel Nenni on 05-15-2020 at 6:00 am
Categories: EDA, Events

The foundation of SemiWiki.com has always been to transition live semiconductor related events to an easy to digest digital format via a worldwide online semiconductor community. SemiWiki is staffed by working semiconductor professionals that transform live events, press releases, whitepapers, webinars and other collateral into easy to read blogs for the semiconductor ecosystem.

Since going online in 2011, SemiWiki has published more than 7,000 blogs (in collaboration with our sponsors) that have garnered more than 42,000,000 views. As a result, SemiWiki in total has experienced more than 3,400,000 users and is the #1 semiconductor ecosystem portal around the world.

I have worked with dozens of marketing teams through SemiWiki over the last ten years and the one that stands out is the former eSilicon team of Mike Gianfagna and Sally Slemons. In regards to quality of results Mike and Sally are the best of the best which is why I have asked them to join me in this webinar, absolutely.

REGISTER HERE

The 2020 pandemic has accelerated the move to digital content so the multi-billion dollar question is: How do we thrive during this transition?

In this webinar you will learn:

What tools and resources are available
How to repurpose your live event budget for maximum impact
How to create great content
How to find new ways to get your content in front of customers
How to maximize your reach
How to fully monetize this process

For smaller companies, this unexpected change in the marketing landscape can actually be an opportunity. In the digital world the playing field is much more level. You can get your message out in a way that you couldn’t at a live event, operating from a ten-by-ten booth across the aisle from your 500-pound-gorilla competitor in a 50-by-50 booth with an espresso machine next to their 30-seat theater.

Join us for a lively discussion about how to market your company in this new, virtual environment. You may be surprised at the options available to you.

MODERATOR:
Daniel Nenni is the Founder of SemiWiki.com, the Open Forum for Semiconductor Professionals. Daniel is an internationally recognized semiconductor ecosystem expert, public speaker, author and publisher, and was a professional blogger even before blogging was a profession.

PRESENTERS:
Mike Gianfagna is a principal at Gforce Marketing, an independent marketing consulting company. He is also a staff blogger for SemiWiki.com. Previously, Mike was a semiconductor and EDA executive. He offers demonstrated achievements in ecommerce, cloud migration, product launch, company branding and multi-tier communication strategies.

Sally Slemons is an independent marketing consultant at Noise! Marketing Communications. She brings 25 years of semiconductor industry marcom experience to help companies ideate, orchestrate, and execute integrated, results-oriented B2B marketing programs. She is skilled at making small technology companies look big and big technology companies look brilliant.

REGISTER HERE