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What’s Wrong with Robotaxis?

What’s Wrong with Robotaxis?
by Roger C. Lanctot on 08-08-2022 at 6:00 am
Categories: Automotive
7 Comments

Whats Wrong with Robotaxis

For some reason the obsession with robotaxis persists throughout the world and throughout the transportation industry. The collective conventional wisdom appears to be that getting rid of the human drivers of taxis and letting these vehicles freely operate presumably around the clock will save money and the environment.

Tesla’s Q2 earnings report puts the lie to this ill-placed optimism. While robotaxis are putt-putting around Phoenix, San Francisco, and Shanghai, human driven Teslas have notched 35M miles in “full self-driving” (FSD) Beta mode, according to CEO Elon Musk.

Musk says on the earnings call that FSD Beta with City Streets driving capability has been deployed to more than 100,000 Tesla owners. Commenting on the latest SmartDrivingCars podcast, Princeton’s Faculty Chair of Autonomous Vehicle Engineering Alain Kornhauser expressed his admiration for Tesla’s ability to recruit human drivers (i.e. Tesla owners) to help teach the computers how to drive. Kornhauser went further, estimating the value of the 35M miles of computer-assisted driving to be approximately $100M to Tesla at $3/mile.

Kornhauser is zeroing in on the critical differentiator between Tesla and every other autonomous vehicle developer. By deploying autonomous or semi-autonomous or self-driving technology in privately owned vehicles, Tesla is allowing the humans to teach the computers how to drive.

Musk and Tesla understand that humans are good drivers, in spite of getting a bad rap. Roads from city streets to highways were designed for human operation, so it makes sense to leverage human driving skills to refine the algorithms and fuel the neural networks that are ultimately expected to take over.

In contrast, robotaxis are operating based on rules-based assumptions and a see-plan-act “mindset” that must simultaneously anticipate and react to its driving environment. Robotaxis are essentially being asked, without much help, to understand how humans drive while being mindful of obeying the driving rules.

It’s a hopeless task with little prospect of short-term success. For these and other reasons Waymo is operating in the desert – to eliminate weather concerns – and Cruise Automation is operating at night – to mitigate issues around traffic congestion.

The nearly impossible objective of achieving full self-driving, long-promised by Tesla, is more likely to be achieved by Tesla because of its decision to keep the human “in the loop.” Robotaxis operate on the assumption that the human is the problem – the fly in the self-driving ointment.

This isn’t the only flawed assumption. The second flawed assumption is that robotaxis operated by computers that never become drowsy or tired will be more efficient and therefore lead to reduced emissions and energy consumption.

Based on Waymo’s Q2 data gathered from its operations in California, 92% of the vehicle miles traveled by Waymo vehicles were spent “loitering.” Only 8% of Waymo’s Q2 VMT was consumed carrying passengers or en route to pick up passengers.

The only possible justification would be that the pursuit of robotaxi development is expected to yield valuable insights into solving as yet unidentified transportation challenges. Color me skeptical.

Robotaxis are already having a deleterious impact on urban transit with notable traffic jamming incidents instigated by Cruise in San Francisco. But it is not just the catastrophic failures that are relevant. Robotaxis operated by Cruise and others around the world are adding their own quirks to the existing urban transportation chaos which is still evolving – post-COVID – to accommodate e-bikes and e-scooters, a proliferation of delivery vehicles, delivery drones, and ever-present pedestrians.

Robotaxis are also guaranteed to be more expensive to operate than taxis, while driving more slowly, and lacking the flexibility to travel beyond the city limits via highways.

Yet, for the time being, developers will continue to throw hundreds of millions of dollars (Cruise has a nine-figure quarterly cash burn rate) at robotaxis to solve a problem already adequately addressed by public transit and traditional taxis. Robotaxis are and will continue to be more expensive to operate, slower, more polluting, with a limited operational design domain, and a fundamental inability to equal or surpass existing human driving acumen.

Other than all of that, robotaxis make perfect sense. Send in the clowns.

Also read:

Wireless Carrier Moment of Truth

DSPs in Radar Imaging. The Other Compute Platform

Accellera Update: CDC, Safety and AMS

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KLAC same triple threat headwinds Supply, Economy & China

KLAC same triple threat headwinds Supply, Economy & China
by Robert Maire on 08-07-2022 at 10:00 am
Categories: Semiconductor Advisors, Semiconductor Services

KLA Tencor

-KLA sings same cautionary song as LRCX (with Intel Chorus)
-Sees similar softening of WFE & second half
-Same Government “notice” on China/14NM – Same supply ills
-We remain concerned about share loss in patterning

Deja Vue, all over again- Great QTR & Guide amid caution & softening

KLAC reported a very good result coming in at $2.49B and EPS of $5.81 versus street of $2.43B and EPS of $5.50. Guide is for $2.6B +-$125M and EPS of $6.25+-$0.55 versus street of $2.52 and EPS of $5.81. Management cut their outlook on 2022 WFE to $95B much as we heard from Lam the day before. To a large extent the words on KLA’s call and Lam’s call were almost exact copies…..great numbers clouded by a weakening and cautionary outlook

Its like groundhog day.

Same notice from Government on China and 14NM

KLA got the same memo on China and 14NM. Obviously very lacking in details it sounds a lot like ” be prepared for tougher licensing on China, details to follow”. No details and no commentary other than no impact to numbers (for now…).

Given that China was 29% of KLA’s business we would be very concerned. We think that much like litho tools its important for the government to curtail yield management as they are the learning tools that China needs and much like ASML there aren’t a lot of other sources. This is compared to process tools where there is significant non US competition.

On the positive side we think that most any tools not shipped to China should easily be directly to eager customers not in China so while there may be short term dislocation in the long run the impact from a China embargo will be minimal.

Share loss in patterning remains a problem

Even though management talks about patterning being a lumpy business, we are waiting for a positive lump. The numbers for patterning remain unimpressive and not just due to lumpiness. Patterning was only up 15% year over year and down 20% quarter on quarter while wafer inspection was up a whopping 49% year over year and up 20% quarter over quarter. Wafer inspection was over twice patterning.

We find it very telling that in KLA’s prepared slides they talked about the impressive growth and “leadership” position of wafer inspection but no mention of patterning which is not in a leadership position nor impressive growth.

Demand remains beyond great

Demand is super strong and obviously beyond KLA’s ability to supply. Any holes or push outs or cancelations in the order book can quickly be filled by those customers further down the waiting line. While perhaps not as strong as ASML, KLA is a close second with some product pushing two years out…..

Financials fantastic

It almost goes without saying that KLA has the greatest financial performance in the industry, even better than the monopoly that is ASML. Cash flow and use is great and margins remain super strong.

Supply chain issues appear to be company’s biggest concern

Supply chain issues continue. While they may be getting better they seem more like just constant, ever changing headwinds of one sort or another. It doesn’t seem to have that much if any negative impact on KLA’s numbers but the company obviously is just concerned about getting tools out the door, more or less on time.

We don’t see this issue going away any time soon and will certainly persist for the remainder of the year and well into 2023. Its unclear when will will get back to whatever normal now represents.

Intel cutting spending during KLA’s call

It is somewhat strange that while KLA was on the call talking about potential weakness in memory that Intel was on their earnings call cutting spending. Obviously KLA’s management wasn’t listening to the Intel call but its an interesting contrast in real time.

To be fair, Intel said they were still dedicated to technology spend but we could see delays and/or push outs or other spending changes coming out of Intel and its also likely that those changes last more than a few quarters.

The stocks

If you didn’t listen to the call and just went by the results and guidance, the stock should have been up strongly in the after market, but it wasn’t, clearly the anxiety of the the triple threat of the economy (memory), China and supply chain cast a pall over what should have been a celebratory party on the great results.

The stock market hates uncertainty and we have it in spades. We continue to think that the downside beta far outweighs the upside beta. There is too much to go wrong and we already know how great things are.

There is not a lot that makes us want to go out and buy the stock. The recent bounce seems to be somewhat of a mirage that things will continue to be wonderful and we aren’t headed into a downturn.

In case you think you have seen the the exact same words above before ….you did…you saw them yesterday in our note on Lam. Our feelings on the stock and the stocks reaction are the same as for Lam.

The only difference is the added negative of the Intel bad news which only makes the situation even worse today than yesterday….

If you don’t think we are in a chip downcycle by now you have been living under a rock…..

Yesterday it was Charles Dickens

Tonight its Yogi Berra, “Its Deja Vue all over again”.

About Semiconductor Advisors LLC
Semiconductor Advisors is an RIA (a Registered Investment Advisor), specializing in technology companies with particular emphasis on semiconductor and semiconductor equipment companies. We have been covering the space longer and been involved with more transactions than any other financial professional in the space. We provide research, consulting and advisory services on strategic and financial matters to both industry participants as well as investors. We offer expert, intelligent, balanced research and advice. Our opinions are very direct and honest and offer an unbiased view as compared to other sources.
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‌Also read:

ASML Business is so Great it Looks Bad

SEMICON West the Calm Before Storm? CHIPS Act Hail Mary? Old China Embargo New Again?

 

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The Semiconductor Market Downturn Has Started

The Semiconductor Market Downturn Has Started
by Malcolm Penn on 08-07-2022 at 6:00 am
Categories: Future Horizons, Semiconductor Services

Growth Rate Trends

What we alone said would surely happen, but what was widely denied by the industry, was confirmed with June’s WSTS Blue Book report.  Right on cue with our December 2021 forecast, the current semiconductor Super Cycle is finally drawing to a close and the 17th market downturn has now well and truly started.

The Macro Evidence

At the macro level, the worldwide semiconductor momentum indicator, pictured above, passed through the ‘Death Cross’ in March 2022 signifying storm clouds on the horizon; June’s market data saw the start of the storm.

Anecdotal indication of the downturn has also started to filter into the industry consciousness, especially at the commodity end of the market, with several second-tier foundry houses and IDMs reportedly mulling scaling back or postponing their planned capacity expansions.

Already Global Foundries has warned it expects to see its capacity utilization fall in the second half of the year, due to order cuts by its fabless clients, and Samsung is reportedly suffering a similar impact too.

The downstream knock-on effect on the semiconductor equipment and materials industry has already started to bite, with some firms starting to see second-half year push backs and delays.

PC and smartphone shipments, two key semiconductor market drivers, are both showing declines in the first half of 2022, with PC shipment now reportedly at their lowest level since 2019, and Smartphone shipments expected to show negative growth in 2022.

Products that require specific manufacturing capacities, such as automotive, are still showing signs of tightness, but the end market demand for cars is likely to soften as prospective customers, now squeezed by and struggling with inflation and a massive spike in energy costs, put off buying that new car.

With demand for consumer MCUs, display drivers, power management and other mass-market chips falling, nearly all mature node fabs have seen their customers scale back wafer starts for the second half of 2022 prompting several second- and third-tier foundries to start cutting prices.  Some are even rumoured to be offering fire-sale incentives and cut-price deals for additional wafer orders to maintain their fab utilization rates.

Such actions will, however, we believe, prove fruitless given the industry-wide pressure, and customer need, to offload bloated inventories, built up over the past two years of supply shortages.

Time will tell if customers violate their long-term agreements (LTAs) to ease inventory pressure or, if they do, what actions the suppliers could in reality actually do.

Whilst TSMC is in a better position overall, due to its market dominance especially at the leading-edge – leading-edge capacity is, by definition, always in short supply – it too will not escape the effects of the downturn, given the wide diversity of the end markets it serves.

We believe TSMC will need to tread very carefully indeed here if it is to avoid an inevitable antitrust challenge by its customers and competitors of market exploitation and price gorging if it carries out its plan to raise its prices in 2023 against the prevailing market trends.

Devil’s In The Detail

At the detailed level, monthly IC unit shipments and ASPs shrank sequentially 10.6 and 14.9 percent in June, resulting in a whopping double-digit sales value decline of 23.9 percent.  The comparable numbers for the previous month were all positive at 3.3 percent, 7.8 percent and 11.4 percent respectively.

The inventory correction we cautioned was inevitable is now starting to manifest itself by way of reduced unit shipments with all sectors showing negative monthly growth vs. May.  This was in sharp reversal to May’s unit growth results, which showed all sectors still growing, other than Micro which suffered a modest 0.6 percent decline.

Reduced unit shipments will quickly translate into a sharp cutback in new orders, taking the pressure of fab capacity and eventually shorter lead times, just as the first wave of increased capacity is coming online.

In parallel, IC ASPs fell an eye-watering 14.9 percent in June vs. May, with Memory hit hardest dropping 19.0 percent.  Micro ASPs fell 8.5 percent followed by Logic at 7.2 percent and Analog at 3.7 percent.

Adding to these woes, in its July mid-year report, the IMF reported a gloomy and more uncertain global outlook, downgrading its 2022 GDP forecast from 3.6 to 3.2 percent, with the economic risks now all overwhelmingly tilted to the downside.

It is this combination of negative ASP growth, falling unit shipments, increased capacity and a weak global economy that will tip the semiconductor market into negative growth in 2023.

Market Outlook

Granted, most firms are still reporting strong second quarter results and full order books for Q3/Q4-2022, but, in the same breath, many are now starting to admit that these orders could easily vaporize.

When we published our 6.0 percent growth forecast for 2022, shrinking by 22.0 percent in 2023, in May 2022, we were still the only analyst cautioning that a downturn was imminent.  It might yet transpire even our forecast was optimistic.  Based on a forecast that the second quarter would grow 1.5 percent vs. Q1-2022, with the actual growth coming in at only 0.5 percent, our May 2022 forecast has now been pushed into bear territory.

Whilst we are not yet minded to formally downgrade our forecast, we are even more certain we called the 2022 downturn correctly when we issued our warning at the end of last year.

We will be formally revisiting the numbers for our annual mid-term Industry Forecast Update webinar on September 13 but until then suffice it to say there is now no upside to our 2022 forecast and all industry hopes of double-digit growth for 2022 have been blown out of the water.

For a full analysis, see Future Horizons’ August Semiconductor Monthly Update Report Visit www.futurehorizons.com to sign up for IFS2022-Mid-Term Webinar

Also read:

Semiconductor Crash Update

The Roots Of Silicon Valley

The Semiconductor Shortage False Narrative!

Podcast EP98: How Menta is revolutionizing embedded FPGA deployment

Podcast EP98: How Menta is revolutionizing embedded FPGA deployment
by Daniel Nenni on 08-05-2022 at 10:00 am

Dan is joined by Dr. Yoan Dupret, the Managing Director and CTO of Menta – a leader in embedded FPGA IP cores for chips and smart sensors. Yoan explores the impact Menta’s embedded FPGAs are having on current designs. The reasons for Menta’s success and where the impact will be in the future are both discussed as well.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

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How TSMC Contributed to the Death of 450mm and Upset Intel in the Process

How TSMC Contributed to the Death of 450mm and Upset Intel in the Process
by Craig Addison on 08-05-2022 at 6:00 am
Categories: Foundries, Intel Foundry, TSMC
8 Comments

450mm wafer

Pinpointing exactly when 450mm died is tricky. Intel’s pullback in 2014 has been cited as a pivotal moment because it was the main backer of the proposed transition, as it had been for the shift to 150mm (6-inch) wafers in the early 1980s.

However, the participation of global foundry leader TSMC was also seen as crucial if 450mm wafers were to become reality, as was support from Samsung Electronics and the semiconductor equipment sector, the latter having shouldered the financial burden of the 300mm transition.

Two years after Intel’s pullback in 2014, TSMC quietly wound down its participation in the Global 450 Consortium, founded at SUNY Polytechnic Institute in New York in 2011.

The reported reasons for Intel’s decision were low utilization rates and an empty fab 42 shell, but why did TSMC turn cold on 450mm?

The answer to that question – or at least one interpretation of it – can be found in a newly published oral history interview with Shang-Yi Chiang, TSMC’s vice president of R&D at the time.

Earlier this year, Chiang sat for an interview as part of the Computer History Museum’s oral history program. The transcript of the interview is now available as public record.

“It seemed a foregone conclusion that [TSMC] would go along with the next size… which was aggressively being pushed by Intel,” Chiang is quoted saying in the transcript. “Intel tried very hard to get TSMC and Samsung to join forces. Intel already started spending a couple billion dollars in preparing for 450-millimeter wafers,” he said.

After TSMC’s founder and CEO Morris Chang presented a roadmap for 450mm at an investor conference, “all of a sudden… the industry became very hot for 450mm wafers,” according to Chiang.

However, that’s when the TSMC R&D chief revealed his reservations about the commitment.

“One day in 2013, I think around March… I went to Morris Chang’s office. I said, ‘I don’t think we should promote these 450mm wafers. In the past, our competitors [were] UMC, SMIC, and those guys are much smaller than we are. [If] we promote 450mm, we take advantage of them. But right now, we only have two competitors, Intel and Samsung. Both are bigger than we are.”

Chiang argued that 450mm would tie up too many of TSMC’s R&D staff, reducing its ability to pursue technology advancements in other areas. However, Intel – with a bigger R&D budget – would be less affected. Therefore, the main reason for going to larger wafers was so “a big guy can squeeze the small guy out”, Chiang said.

Subsequently, Morris Chang called more than 10 internal meetings to discuss the matter, but he also dispatched Chiang to consult with equipment vendors, including Applied Materials, Lam Research and KLA.

In the end, the TSMC founder decided not to support the transition to 450mm. However, the problem was how to communicate that decision without sounding “negative”.

“If you just say directly that TSMC will not do that, it is a negative image because you are not looking at the future,” according to Chiang’s interview transcript. Instead, it was decided that the decision would be framed as a shift in priorities. Instead of 450mm, TSMC would focus on “advanced technology”.

Chiang also recounted how he conveyed the decision to Intel’s technology and manufacturing chief Bill Holt. It was at a private meeting at SEMICON West 2013, hosted by ASML and attended by two representatives from Samsung Electronics as well as two each from Intel and TSMC.

Holt opened the meeting by saying he believed the industry should be aggressive in moving to 450mm, and that all the players should share the costs, according to Chiang’s recollection.

Samsung’s representatives did not say anything. When Chiang’s turn came, he gave Holt the bad news, but the Intel manufacturing chief did not take it well.

“He was very upset and walked away,” according to Chiang’s recollection.

Holt, who began his Intel career in DRAM development in 1974, retired from Intel in June 2016.

Chiang, a US citizen whose most recent assignment was with TSMC’s mainland Chinese rival SMIC, retired from the industry last year and now resides in Silicon Valley.

Also read:

Future Semiconductor Technology Innovations

3D Device Technology Development

Three Key Takeaways from the 2022 TSMC Technical Symposium!

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LRCX – Great QTR and guide but gathering China storm

LRCX – Great QTR and guide but gathering China storm
by Robert Maire on 08-04-2022 at 10:00 am
Categories: Semiconductor Advisors, Semiconductor Services
2 Comments

Lam Research Headquarters

-Lam reports record QTR and great guide amid growing anxiety
-Weakness has not yet trickled down to Lam’s order book
-Company contacted by US government on new China restrictions
-Combination of supply issues/China/economy cut WFE view

Numbers are great

Lam reported revenues of $4.64B and EPS of $8.83 which represented a very strong beat. Even more importantly , guidance for September is for $4.9B +- $300M and EPS of $9.50 +- 0.75. Deferred revenue was up slightly from $2.07B to $2.2B.

These are record levels of business…..but despite these records the company cut its year WFE spending view from $100B to $90 to $95B range….obviously this is a strange contradiction, business is great, better than ever yet the company is getting more cautious on the overall yearly outlook.

The triple threat- China embargo, Down cycle & Supply Chain

The problem is that we have three relative unknowns hanging over the industry’s and Lam’s head. The supply chain continues to be a problem even though Lam appears to have done a good job in mitigating those issues. There clearly is a down cycle happening in the memory segment as reported by several chip makers in the memory market. Lam being a memory centric provider is more susceptible than other tool makers to a memory downturn. We have not seen similar signs in foundry/logic…..yet. And last, but not least in the triple threat is China….

Lam has been contacted by the US government on China embargo

Lam management said;

“we were recently notified that there was like – there was to be a broadening of the restrictions of technology shipments to China for fabs that are operating below 14-nanometer. And so that’s the change I think that people have been thinking might be coming. And our – we’re prepared to fully comply. We’re working with the U.S. government and any impact on Lam’s business it’s contemplated in the September guidance that we just gave.”

So the impact, reductions, in Lams business, have already been calculated into September guidance and the company also said that China impact is part of their reduction of overall annual WFE spend.

Management said fabs operating below 14NM which is only SMIC and then not really in any volume. We think management misspoke, we think the impact is on tools capable of below 14NM not fabs as it would be stupid for the government to allow some fabs in China to get sub 14NM tools while others can’t.

With China representing 31% of Lam’s business, that could be a significant impact. China is by far, Lam’s biggest market with Korea second at only 25% and the US a distant fourth after Taiwan. However it sounds like the details remain fuzzy as to the full impact and the company did not clarify further.
This would obviously impact higher revenue, higher value and higher margins tools sold in China.

We are sure the company is fighting and lobbying this issue as it will have a huge impact. We view this as a much bigger threat than supply chain issues which will eventually work out and perhaps even a cyclical downturn which will eventually resolve. An embargo on China could be very long lasting as it was in the past (which few remember).

This also reflects exactly what we have been saying for a long time…that the US can’t ask ASML not to ship tools to China while US companies continue to ship….This will clearly impact Applied Materials and KLA as well and likely KLA to a greater extent given what they sell is aimed at improving yields and getting down the Moore’s Law curve faster. Do as I say not as I do…doesn’t work.

All the words & body language points to a down cycle (at least in memory)

A large part of Q&A seemed aimed at “what if” a down turn rather than “what if” continued growth….It feels like everyone knows there’s a down cycle coming, we just haven’t seen any hard evidence of it yet, in the form of cancelations or push outs and if there have been any weakness it has been covered up by the continued momentum of strong demand.

If we were only talking about a foundry/logic semiconductor industry, we don’t think the tone would be the same as most all the reported issues have been in memory. The big question is will the economic headwinds get strong enough to slow foundry/logic as well? Or could a China embargo be the catalyst of the foundry/logic slowdown that would join the coming memory slow down? Maybe its both.

It seems a bit like the Borg…..resistance is futile….the down cycle is coming

Supply chain remains an issue but least of our concerns

The company still has supply chain issues but has also clearly made progress. While it continues to weigh on the September and WFE outlook its more of a delay and minor headwind than a cyclical down turn or technology embargo.

We don’t want to make light of it as the management likely spends most of its time on supply chain issues as there is not a lot they can do directly on China or a global macro economic down turn….but it is something they can and do impact

The stocks

If you didn’t listen to the call and just went by the results and guidance, the stock should have been up strongly in the after market….but it wasn’t ….clearly the anxiety of the the triple threat of the economy (memory), China and supply chain cast a pall over what should have been a celebratory party on the great results.

The stock market hates uncertainty and we have it in spades.

We continue to think that the downside beta far outweighs the upside beta. There is too much to go wrong and we already know how great things are. There is not a lot that makes us want to go out and buy the stock. The recent bounce seems to be somewhat of a mirage that things will continue to be wonderful and we aren’t headed into a downturn.

We think perhaps the most important data point on the call wasn’t in the prepared remarks and was glossed over…perhaps on purpose….that Lam was “notified” by the US government about China…..words you never want to hear “notified by the government”.

We can only imagine that now Applied and KLA will have to answer that same question on their calls and will likely give the same answer that they too were “notified” and that it is negatively impacting their outlook

It may take investors some time to figure out that AMT and KLA will say similar things on their calls, so their stocks should be off in sympathy as even higher percentages of their business are from China.

We see this as more negative news for the group and the beginning of confirmation of some of our concerns re China as Lam was the first to talk about it.

I can’t help but think back to my grammar school Charles Dickens, reading a “Tale of Two Cities”….”it was the best of times (for revenue and earnings) it was the worst of times (for anxiety and fear of a downturn).

About Semiconductor Advisors LLC
Semiconductor Advisors is an RIA (a Registered Investment Advisor),
specializing in technology companies with particular emphasis on semiconductor and semiconductor equipment companies. We have been covering the space longer and been involved with more transactions than any other financial professional in the space. We provide research, consulting and advisory services on strategic and financial matters to both industry participants as well as investors. We offer expert, intelligent, balanced research and advice. Our opinions are very direct and honest and offer an unbiased view as compared to other sources.

Also read:

Intel & Chips Act Passage Juxtaposition

ASML Business is so Great it Looks Bad

SEMICON West the Calm Before Storm? CHIPS Act Hail Mary? Old China Embargo New Again?

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DSP IP for High Performance Sensor Fusion on an Embedded Budget

DSP IP for High Performance Sensor Fusion on an Embedded Budget
by Kalar Rajendiran on 08-04-2022 at 6:00 am
Categories: EDA, Events, IP, Synopsys

VPX Vector DSP Core Data Types

Whether we realize it or not, everyday applications we use depend on data gathered by sensors. We can bet that pretty much every application uses at least a couple of different types of sensors, if not more. That is because different types of sensors are better suited to collect data depending on the application, the environment from which data is to be gathered, whether it is daytime or night, etc. Many times, many different types of sensors are used to gather data for the same application because depending on just one may be unreliable. This is where the concept of sensor fusion comes in. Sensor fusion means combining data from multiple sensors to obtain complete, accurate and reliable results. It enables context awareness and new user experiences.

This process relies on lot of processing algorithms and is very taxing on the software. Of course, hardware doesn’t have a cake walk in this respect. More times than not, the algorithms have to be implemented in a special purpose chip rather than running on a general purpose processor. The ever present demanding requirements of PPA pushes applications to implement sensor fusion in an optimized hardware/software solution.

Recently, Synopsys hosted a webinar titled “DSP IP for High Performance Sensor Fusion on an Embedded Budget.” The keywords in the title are “embedded” and “budget”. As we all recognize, many of the fast growing applications of today are embedded in nature. These applications demand very high performance, compact implementation and low power consumption. At the same time, the business requirements are even tighter in terms of price points and time to market expectations.

This post covers some salient points from the webinar. You may already be part of a team that is implementing a sensor fusion solution for an end application among the many that depend on multiple sensors. Or you may soon be. Irrespective, this webinar is a very useful one for you to watch. Pieter van der Wolf, Principal R&D Engineer at Synopsys presented the webinar. It is available for viewing on-demand here.

Sensor Fusion Trends

Smart mobile, automotive systems, smart home systems, health and industrial control are some of the markets leveraging and benefitting from the use of multiple sensors. MEMS technology for miniaturization and the lower cost of sensors are rapidly fueling the innovations in the sensor fusion space. At the same time, the requirements for even a pedometer application covers a wide range of sensors. The use of different sensors in wearables to virtual assistants to automotive radar/LiDAR – requires SoCs to have an optimal balance of performance and low power/area. As no single type of sensor is perfect for every application, sensor fusion is key for accurate and reliable results. The key tasks of sensor fusion includes localization, mapping and path planning. Localization is to determine the “where am I?” component. Mapping is to determine the “what’s around me?” based on the model of expected environment with objects and their properties. And the Path Planning is to determine the “what to do next?” action decision.

DSP IP for Sensor Fusion Solutions

SoC architectures must be able to scale easily with fast changing requirements from applications. The SoCs must also be versatile enough to handle varying workloads and data types. Building from scratch for every new variant or future version of a product is not practical. A DSP lends itself nicely to accommodate these requirements.

Scalability

A pedometer application requires about 10 MIPS while an autonomous driving application needs 10 TOPS or higher. A scalable, software-compatible family of DSP IP can serve well to implement a range of sensor fusion applications, while enabling re-use of the software across all these SoCs.

Versatility

A microphone data stream is of 16-bit integer data type, a camera data can either an 8-bit or 16-bit integer type but a radar data type could be either integer or floating point at 16 or 32 bits. The architecture and the implementation should be versatile enough to handle all these data types and allow the compute resource to be shared among a mix of workloads.

SoC-level Challenge

An SoC must support efficient data movement through fast DMA to peripherals and system memory. The SoC implementation should also be resilient to high memory latencies. It should deliver a high Fmax for required cycle performance at the same time enable easy timing closure. And of course, the low power consumption, low leakage, small form factor and low-cost are requirements that go hand in hand with these applications.

Don’t Forget the Software

Sensor fusion solutions are not just about hardware optimization. They require development and integration of a variety of software modules for data processing, user interaction, interrupt handlers, drivers, etc., The software code should be easily portable across different DSP IP implementations.

Synopsys’ Offerings for Implementing Sensor Fusion Solutions

Efficient SoC Integration

Synopsys offers an entire family of DSP IP to serve various markets. For sensor fusion applications, the ARC® VPX family of processors is the right match. It is easy to scale an implementation using the pre-integrated multicore DSPs with cache coherency and shared DMA. Whether the SIMD implementation is 128-bit, 256-bit or 512-bit, there is a corresponding processor in the VPX family to support that requirement. There is also the ARC NPX NN accelerator that can be used under the unified programming environment to implement the front-end for ML applications. The VPX processors are highly configurable to achieve performance/area optimizations. These processors also support a variety of data types.

Extensive Set of Software Building Blocks

Synopsys offers a rich set of software building blocks including the Vector DSP library and the Vector Linear Algebra library. These libraries are implemented using Vector-Length Agnostic C/C++ programming model, enabling easy software portability across all members of the VPX family. Also included are the machine language interface library and the NN software development kit.

Summary

In summary, the Synopsys ARC VPX DSP processors offer high performance and scalability, compact form factor, and low power. These processors are compliant with the ISO 26262 ASIL B/D level requirements for automotive safety requirements. Heterogeneous signal-processing workloads can be efficiently and effectively implemented using these processors. It is also easy to integrate with processors from the other members of the Synopsys ARC family of DSP processors.

You can learn more details about the Synopsys ARC VPX DSP Processors here.

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SEMICON West 2022 and the Imec Roadmap

SEMICON West 2022 and the Imec Roadmap
by Scotten Jones on 08-03-2022 at 10:00 am
Categories: Events, Semiconductor Services, TechInsights

ITFUSA2022 LucVandenhove Page 093

SEMICON West 2022 was held from July 12th to 14th at the Moscone Center in San Francisco.

On Monday the 11th before the show, Imec held a technology forum at the Marriott Marquee right around the corner from the Moscone center. In recent years the Imec forums have shifted away from the process technology I cover to more of a system and application forum but there is still some process content.

During Luc Van den hove’s talk he presented the roadmap slide shown as figure 1.

Figure 1. Imec roadmap.

For all the talk in certain circles about the death of Moore’s law, the Imec roadmap presents over a decade of continued logic scaling.

At the N2 node Imec shows the transition to Gate-All-Around (GAA) nanosheets, this is underway now with Samsung introducing GAA nanosheets for their 3nm node and Intel and TSMC announcing GAA nanosheets for 2nm (Intel 20A). After two generations of nanosheets, Imec has a transition to Forksheets. Forksheets are a variant of nanosheets that reduces the track height of the cell. At this time, it isn’t clear to me how much traction Imec’s Forkseheet proposal is getting at the device manufacturers, I really haven’t seen any work on Forksheets outside of Imec. After two generations of Forksheet’s Imec has CFETs taking over. There is a lot of work being done on CFETs notably at Intel and TSMC. The last generation of CFETs introduces atomically thin sheets.

In Geert Van der Plas’ talk some more details were presented on the potential roadmap.

Figure 2 presents the transistor density that would result from the roadmap shown in figure 1.

Figure 2. Imec roadmap transistor density.

 As can be seen in figure 2., although density continues to increase the rate decreases to 1.2x to 1.3 per node.

Figure 3 presents some additional detail on the scaling roadmap with standard cell, backside, back-end-of-line and CMOS 2.0 innovations. Standard cell scaling is increasingly driven by Design-Technology-Co-Optimization (DTCO) such as single diffusion break, contact over active gate, forksheet wall, etc. The backside of the wafer is becoming a critical part of scaling with backside power delivery. BEOL will require new materials and patterning techniques to support the denser devices.

Figure 3. Transistor scaling innovations.

Figure 4 illustrates some options for the backside of the wafer, not only providing backside power delivery but also possibly incorporating active devices as well.

Figure 4. Backside options.

 On Tuesday morning I attended the “Unique Challenges Associated with Manufacturing 3D Devices and Structures Including GAA, 3D DRAM and 3D NAND” tech Talks moderated by Linx Consulting.

I only caught the end of the first speaker Nabil Mistkawi of Samsung’s talk, but I thought it was very interesting when he said at 7nm and below drying can require five steps to prevent pattern collapse, this really illustrates the fabrication difficulties presented by leading edge technologies.

Ian Brown of Screen went into more detail on pattern collapse and cleaning and drying challenges at the leading edge.

For logic devices shallow trench isolation/fin formation and post poly etch are critical steps. Nanosheets add a lot of surfaces some of them hidden and horizontal nanosheet release is very critical. 3D NAND silicon nitride removal needs to be a fast process, but you have to avoid silicon dioxide precipitation. DRAM active and capacitor formation are very critical.

Laplace pressure and surface tension can cause 3D structures to collapse. Spin dryers have been replaced with IPA dryers, but they are sensitive to surface state. Today modifying a hydrophilic surface to make it hydrophobic before drying is state-of-the-art for logic.

In the early days of the industry particles were removed by etching underneath them, then there was a transition to megasonics but below 65nm there were damage issues. Today spin cleaners are used but they can create damage if the pressure is too high. The best technique for drying currently available is super critical CO2 but it is slow and expensive due to the equipment cost.

Finally, Aviram Tam of Applied Materials discussed inspection and metrology challenges. 3D structures need a technique that can look into the structure. High energy eBeam offers the ability to look into a structure and characterize the structural dimensions versus depth. With the advent of EUV optical overlay is no longer accurate enough and eBeam is being looked at here as well.

Following the session, I walked the floor. The show has really shrunk from the days when it filled both the North and South Halls with this years show not using the South Hall. On Tuesday a lot of vendors were sitting in their booths with little or no traffic staring at their phone screens.

I walked the floor again Wednesday and there was a lot more traffic in the booths.

New York state had a big booth at the show and one thing that surprised me was the number of people in that booth both days, I mean how many people can be thinking about building a fan in New York?

Thursday I travelled back home.

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Podcast EP97: Unlocking the Future of Innovation with Graphene

Podcast EP97: Unlocking the Future of Innovation with Graphene
by Daniel Nenni on 08-03-2022 at 8:00 am

Dan is joined by Paul Hedges, CEO and co-founder of graphene and 2D materials specialists, Applied Nanolayers. Paul explains how wafer-scale integration of materials like graphene can be accomplished, unlocking new “more than Moore” applications such as biosensing and photonics. The applications Paul describes are quite impressive and include deployments in space.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

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NoC-Based SoC Design. A Sondrel Perspective

NoC-Based SoC Design. A Sondrel Perspective
by Bernard Murphy on 08-03-2022 at 6:00 am
Categories: Aion Silicon, Semiconductor Services

NoC optimization min

Why are NoCs important in modern SoCs and what are best design practices for using NoC? As always, a great place to start is the perspective of an SoC design organization which depends on pumping out high performance designs. Sondrel is a turnkey ASIC service provider, covering the spectrum from system design to silicon supply. Clearly doing well since they have created designs now in production in hundreds of products in mobile, security, AR/VR and other applications. Drawing on this experience they recently released a white paper detailing their rationale for depending on Arteris FlexNoC interconnect and their approach to NoC floorplan and performance optimization.

Why choose a NoC and why FlexNoC?

Interestingly, for Sondrel “Why a NoC?” isn’t even a question that needs to be asked. I would guess that they have already had more than enough experience with the congestion, timing closure and other problems that come with crossbar-based networks in large SoCs.

Why FlexNoC versus an existing in-house network generator? Sondrel cite packetization and serialization in the transport layer, providing them the ability to precisely control where they can reduce wiring and area without compromising performance. They also cite the ability to create a physically aware design even at a very early stage and control over managing power within the network. Perhaps an in-house network could be adapted to provide similar capabilities? In my view, not really. The basic architecture of a NoC is fundamentally different from a crossbar or anything derived from a crossbar. Adapting would be more like redesigning from scratch. I would guess that Sondrel would not consider this a realistic option.

Where does NoC design start?

I’ve always wondered about where NoC design starts. Do you go for design for traffic optimization first, then floorplan, or the other way round? According to Sondrel either approach can take a while to converge. They start instead with architectural performance exploration. This is used to decide on an appropriate size for the interconnects and memory subsystem by modelling the memory traffic patterns that are generated by all the subsystems as if they were running on the real system (to a reasonable approximation). Here I believe they start with spreadsheet estimation, then move to SystemC modeling with channels for connectivity.

Once this step has converged, then they start running real trials on NoC RTL. This is generated to match the goals of the performance exploration. This they do using a proprietary testbench called Performance Verification Environment. The RTL connects to transactors modeling processors and subsystems defined in Python. In this flow Python generates memory-mapped bus traffic is generated and drives it through the NoC. Allowing the NoC architect to quickly see what is going on in the design and how changes will improve the data traffic flow.

In this flow, the NoC definition starts from an already converged architectural performance goal. From Sondrel’s perspective it is then much easier to fine tune the NoC for performance and floorplan deltas. Avoiding major oscillations in the plan. It is also easier to adjust the NoC architecture as needed in response to spec updates. Just as important, providing feedback to their customers on likely impact of those changes on key performance metrics.

You can learn more about Sondrel HERE.

Also read:

Closing the Communication Chasms in the SoC Design and Manufacturing Supply Chain

SoC Application Usecase Capture For System Architecture Exploration

Sondrel explains the 10 steps to model and design a complex SoC