The media has gone wild over a false report that Intel and TSMC are slowing down 3nm. It is all about sensationalism and getting clicks no matter what damage is done to the hardworking semiconductor people, companies and industry as a whole. And like lemmings jumping off a cliff, other less reputable media outlets perpetuated this false report with zero regard for the truth.
By the way, lemmings only jump off cliffs when they become overpopulated and migrations end badly. So maybe that is what has happened here, media outlets have become over populated.
For the record:
“CC Wei: Next, let me talk about the tool delivery update. As a major player in the global semiconductor supply chain, TSMC work closely with all our tool supplier to plan our CapEx and capacity in advance. However, like many other industries, our suppliers have been facing greater challenges in their supply chains, which are extending toward delivery lead times for both advanced and mature nodes. As a result, we expect some of our CAPEX ($4B of $44B) this year to be pushed out into 2023.”
And an update on N3:
“CC Wei: Now let me talk about the N3 and N3E status. Our N3 is on track for volume production in second half of this year with good yield. We expect revenue contribution starting first half of 2023, with a smooth ramp in 2023, driven by both HPC and smartphone applications. N3E will further extend our N3 family with enhanced performance, power and yield. N3E will offer complete platform support for both smartphone and HPC applications. We observed a high level of customer engagement at N3E, and volume production is scheduled for around 1 year after N3. Our 3-nanometer technology will be the most advanced semiconductor technology in both PPA and transistor technology when it is introduced. Thus, we are confident that our N3 family will be another large and long-lasting node for TSMC.”
Yes, Intel had a challenging quarter and it will be a difficult year but my sources say that Meteor Lake, the first disaggregated chip with an Intel 4 CPU, TSMC N3 GPU, and a TSMC N5 base die and SoC is on track. Saphire Rapids I do not know. Since this involves stitching multiple Intel CPU tiles together there could be challenges but this seems to be a design/integration issue versus a process yield problem.
Pat Gelsinger has fixed the Intel process issues by changing the methodology to match what TSMC does, half nodes versus full nodes for advanced yield learning. As a result, I have complete confidence in Intel 4 and 3 moving forward as planned, absolutely.
Pat Gelsinger: For example, regaining our leadership begins with Moore’s Law and the capacity to deliver it at scale. Over the last 18 months, we’ve taken the right steps to establish a strong footing for our TD roadmap. We are well into the ramp of Intel 7, now shipping in excess of 35 million units. Intel 4 is ready for volume production in second half of this year and Intel 3, 20A and 18A are all at or ahead of schedule.
Pat also reorganized Intel design groups and decentralized them for increased autonomy. This will take time to see the results but I can assure you it was the correct thing to do.
I know having chicken little in the semiconductor hen house is fun to watch but it really is getting old. Check your sources and if they have zero semiconductor experience I would take it for what it is worth, entertainment.
And for those of you who want to know what really caused the automotive chip shortage:
“In the past two years they call me and behave like my best friend,” he told a laughing crowd of TSMC partners and customers in Silicon Valley recently. One automaker called to urgently request 25 wafers, said Wei, who is used to fielding orders for 25,000 wafers. “No wonder you cannot get the support.” CC Wei, TSMC Technical Symposium 2022.