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Generative AI for Silicon Design – Article 1 (Code My FSM)

Generative AI for Silicon Design – Article 1 (Code My FSM)
by Anshul Jain on 10-24-2023 at 10:00 am

Generative AI for Silicon Design

In today’s fast-paced world, innovation in semiconductor design is a constant demand. The need for quicker, more accurate, and innovative solutions has paved the way for exploring the potential of Generative AI (#GenerativeAI) in the realm of semiconductor design development. Can it be done? Hell yeah! In this article series, we delve into exciting experiments that demonstrates how Generative AI is revolutionizing semiconductor design.

Experiment 1 – FSM Diagram to SV Code

This first experiment showcases the remarkable capabilities of Generative AI by converting a Finite State Machine (FSM) diagram into SystemVerilog (SV) code. In this case, Google’s Generative AI Model – BARD was used to generate a SystemVerilog implementation of a vending machine FSM shown in the cover picture (sourced from https://www.softwareideas.net/fsm-finite-state-machine-diagram)

FSM Diagram of a Vending Machine

Generated Code

// Vending machine FSM
// Disclaimer: This code is not tested for correctness

module vending_machine (
  input clk,
  input reset,
  input coin_inserted,
  input product_selected,
  input product_dispensed,

  output reg dispense_product,
  output reg return_coin
);

  // Define the states
  localparam [2:0] IDLE = 3'b000;
  localparam [2:0] COIN_INSERTED = 3'b001;
  localparam [2:0] PRODUCT_SELECTED = 3'b010;
  localparam [2:0] PRODUCT_DISPENSED = 3'b011;
  localparam [2:0] OUT_OF_STOCK = 3'b100;

  // Define the registers
  reg [2:0] current_state;

  // Transition logic
  always @(posedge clk or posedge reset) begin
    if (reset) begin
      current_state <= IDLE;
    end else begin
      case (current_state)
        IDLE: begin
          if (coin_inserted) begin
            current_state <= COIN_INSERTED;
          end else begin
            current_state <= IDLE;
          end
        end
        COIN_INSERTED: begin
          if (product_selected) begin
            current_state <= PRODUCT_SELECTED;
          end else begin
            current_state <= COIN_INSERTED;
          end
        end
        PRODUCT_SELECTED: begin
          if (product_dispensed) begin
            current_state <= PRODUCT_DISPENSED;
          end else if (out_of_stock) begin
            current_state <= OUT_OF_STOCK;
          end else begin
            current_state <= PRODUCT_SELECTED;
          end
        end
        PRODUCT_DISPENSED: begin
          current_state <= IDLE;
        end
        OUT_OF_STOCK: begin
          current_state <= IDLE;
        end
      endcase
    end
  end

  // Output logic
  always @(posedge clk) begin
    case (current_state)
      PRODUCT_DISPENSED: begin
        dispense_product <= 1'b1;
      end
      default: begin
        dispense_product <= 1'b0;
      end
    endcase
  end

  always @(posedge clk) begin
    case (current_state)
      OUT_OF_STOCK: begin
        return_coin <= 1'b1;
      end
      default: begin
        return_coin <= 1'b0;
      end
    endcase
  end

endmodule

FSM diagrams are widely used in silicon design, and here’s how Generative AI can play a pivotal role:

  1. Increased Productivity: With Generative AI, creating and updating diagrams becomes a breeze. Designers can now focus on high-level concepts and let the AI do the groundwork. This not only accelerates the development process but also allows for swift iterations when design changes are required.
  2. Higher Accuracy: FSM diagrams have become standardized tools in hardware design. Generative AI models are trained on a vast dataset, making them proficient in converting these diagrams into accurate SV code. The result is reduced human error and higher code quality.
  3. Improved Innovation: Generative AI’s speed and accuracy open doors to rapid exploration of new design ideas. Designers can brainstorm and experiment with various FSM diagrams, pushing the boundaries of innovation. This agility allows for quicker integration of advanced features in each generation of semiconductor devices.

Caution – A Reality Check

While Generative AI holds enormous promise, it’s essential to exercise caution. The generated code may not always be perfect. Designers must review and rigorously test the AI-generated code before deploying it in a production environment. A thorough validation process is crucial to ensure the reliability and functionality of the final semiconductor design.

Conclusion

Generative AI is a game-changer in semiconductor design development. Experiment 1 clearly illustrates its potential by simplifying the conversion of FSM diagrams into SV code, offering increased productivity, higher accuracy, and a boost in innovation. However, it’s vital to remember that AI-generated solutions should be used as a tool to enhance the creative process, not replace it entirely. With the right checks and balances, the synergy between human ingenuity and Generative AI can lead to groundbreaking developments in the semiconductor industry.

Also Read:

Generative AI for Silicon Design – Article 2 (Debug My Waveform)


SRAM design analysis and optimization

SRAM design analysis and optimization
by Daniel Payne on 10-24-2023 at 6:00 am

SRAM design cell min

Every year EDA vendor MunEDA hosts a user group meeting where engineers present how they used automation tools to improve their IC designs, and one presentation from Peter Huber of Infineon caught my attention, it was all about SRAM design optimization. Peter has authored papers at IEEE conferences and been issued patents related to SRAM design. The schematic for a six-transistor SRAM cell is shown below:

SRAM bit cell. Source: Wikipedia

During a SRAM read cycle the Word Line (WL) goes active, then the stored bit values get transferred to the Bit Lines (BL), and finally a sense amplifier goes active to read out the differential Bit Lines. The delay between WL and BL is part of the Read Programmable Self-Timing (RPST), and is tuned by the circuit designer.

SRAM memory designers have several challenges to meet while optimizing the circuit design and layout:

  • Minimum operating voltage, Vmin
  • Sensitivity to small transistor geometries
  • Process variation effects
  • Power consumption
  • Layout density
  • Soft error rate

As the power supply value of Vdd is lowered then the SRAM bit cell eventually fails to operate, and that failure can occur during a Read cycle, Write cycle, or just by noise induced from nearby circuits switching. Influences on the memory failures come from how the core and periphery layouts are done, process and local variations, temperature, memory array size, and the yield criteria.

Yield prediction by simulation is challenging because multiple blocks are involved: bit cell and periphery such as sense amplifiers, multiplexers, self-timing circuitry, and so on. The SRAM designer hence faces multiple issue with parametric yield simulation:

  • The interactions between the blocks are relevant: A bit cell whose read current is exceptionally weak due to local variation of Vth may or may not be read correctly depending on the offset of the connected sense amplifier and other periphery, which in turn depends on the local Vth variation in those blocks.
  • Various blocks’ quantities must be considered, for example in an array of 32 sense amplifiers, each of which is connected to 1024 bit cells.
  • High effort of transient simulation of a single bit cell read cycle, because the transient simulation has to include layout parasitic effects of a large part of the circuit with high accuracy.
  • The statistical analysis must be repeated many times to analyze the effect of array size, macro settings for the self-timing, assist and boost circuitry.

Brute force Monte Carlo SPICE simulation of every cell’s read cycle in an extracted post-layout full chip netlist allows to calculate the statistically correct yield estimate but at a prohibitively large simulation effort. In the past, ML surrogate models could be used to guide the sampling but that still has a too large simulation effort for extensive analysis of the effects of SRAM macro settings.

Infineon now introduced a new two-step approach to simulate their SRAM design by using Worst Case Distance (WCD).

The WCD analysis consists of creating a simulation set with the WiCkeD tool for one Vdd and one probability plus sigma combination.  During this process the worst-case value for Read current (Iread) is determined, and then determining the worst-case sense-amp detuning. Finally, one transient simulation is run for each Programmable Self Timing (PST) setting, with back-annotated worst-cases cells from WCD analysis.

Separating the analysis into two steps has the advantage that the detailed statistical analysis of the sub-blocks is done independently in small netlists with short simulation time, whereas only a handful of slow transient runs of the full circuit are necessary to determine whether the combined worst-case blocks pass or fail the read cycle depending on different high-level macro settings (RPST).

In the past, a single combination of worst-case blocks was used for full-chip transient simulation, for example a 6-sigma worst-case bit cell combined with a 4-sigma worst-case sense amplifier. That was fast and sufficient for verification but overly pessimistic. In the new approach, multiple combinations are tested, and each single met point on the equi-probability curve guarantees a minimal total yield, so that one met point is enough to guarantee the yield and accept the supply voltage as working. In this way, the pessimism is eliminated so that simulated failure rates match very well with silicon measurements.

SRAM equi-probability curves

Simulation results produced the following plot where the Vmin value is on the Y-axis, and the read PST setting is on the X-axis.

Silicon measurements correlated very well with simulations, where the values for Vmin on Read and Write cycles were less than two percent off, as expected due to effects such as IR drop.

Summary

This group at Infineon was able to simulate and optimize Vmin operation values for SRAM designs by using a two-step methodology with the MunEDA WiCkeD tools: WCD plus transient simulation.  Python scripting was used to automate these analysis methods, and that feature is called GangWay.  With scripting they are able to setup and transfer to new memory architectures, reproduce simulation results quickly and transfer the verification task to other engineers.

WEBINAR:  Fast and Accurate High-Sigma Analysis with Worst-Case Points

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Managing IP, Chiplets, and Design Data

Managing IP, Chiplets, and Design Data
by Daniel Payne on 10-23-2023 at 10:00 am

Managing IP min

Design re-use has enabled IC design teams to create billion-transistor designs where hundreds of IP blocks are pre-built from internal or external sources. Keeping track of where each of these IP blocks came from, what their version status is, managing IP, or even discerning their license status can be a full-time job if tracked by manual methods. Other big questions that need to be answered are where to find the right IP, or how to make others aware that you’ve created new IP that could be re-used on new projects.

Companies like Cliosoft, now part of Keysight EDA, have been automating features for IP reuse like finding IP, creating new IP, and safely reusing IP in systems for many years now. A webinar on November 1st at 10:00AM PT is planned, Mastering the Art of Managing IP, Chiplets and Design Data.

The basic SoC design flow will be reviewed in the webinar, along with the multiple engineering roles that form the design and verification team. Having a way for each of these team members to communicate and collaborate during the project ideation and implementation is crucial for success.

IC Design Flow and Team Members

Finding the right IP block either in-house or from third-party vendors is automated with the Keysight IP Management (HUB) tool. System architects typically partition a complex design into smaller pieces using hierarchy as an abstraction, then identify all of the IP blocks required. The members of the design and verification teams may be geographically dispersed, causing communication and documentation challenges. Proper data management tools help with these tasks of partitioning an electronic design, securing the needed IP blocks, and even geofencing IP to conform with license agreements.

Managing IP across geographies

In the webinar both the SoC flow and Chiplet design flows are addressed in terms of managing IP and design data. Common challenges for system design include managing the BOM, IP version conflict resolution, assembly of IP subsystems, safely connecting IP blocks to a NoC, reusing design knowledge of connecting to NoCs.

A team member may update the status of an IP block by attaching a tag to that block, like Verification Ready, then automatically informing other team members of the status change, so everyone knows the history and sequence of who has worked on each IP block, and what the next step is in the design flow. An engineer may tag an IP block as RTL Signoff, then a workflow triggers a snapshot or version made of that hierarchy used for future audits, and finally sends emails to all stake holders. Industries like the DOD and Aerospace have rigorous requirements on tracking specifications and requirements into implementation, so running audits is required for traceability.

Legal teams are also interested in knowing which IP is included in every design that is shipped, so that they can properly manage contract agreements for licensed IP blocks.

The Cliosoft tools are fully integrated in the Keysight EDA tool flow, along with IC tool flows from Cadence and Synopsys. EDA tool users stay within their favorite vendor tool to access all the Data Management (DM) features, making for a quick learning curve. Project management tools like Jira are also integrated, along with bug tracking tools like Bugzilla.

Summary

Attend the webinar on November 1 at 10:00AM PT to learn more about data and IP management, even managing the engineering lifecycle from chip specification all the way to tapeout. Both SoC and chiplet design approaches benefit from using automation beyond what a typical PLM system can provide.

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Podcast EP189: A Look at the Q2 Electronic Design Market Data Report Results with Wally Rhines

Podcast EP189: A Look at the Q2 Electronic Design Market Data Report Results with Wally Rhines
by Daniel Nenni on 10-23-2023 at 8:00 am

Dan is joined by Dr. Walden Rhines. Wally is a lot of things, CEO of Cornami, board member, advisor to many and friend to all. For this discussion he is the Executive Sponsor of the SEMI Electronic Design Market Data report.

Dan explores the Q2 results summarized in the report with Wally. Overall growth was around 5%, a much lower number than prior quarters. Digging into the data a bit Wally points out that the EDA segment of the market continues to show very strong growth. What is different this quarter is a lower growth for IP. Wally believes this is due to a re-classification of revenue that will normalize in subsequent quarters.

Dan explores more detailed analysis of the data from around the world with Wally, including some very interesting regional trends in this informative discussion.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.


100G/200G Electro-Optical Interfaces: The Future for Low Power, Low Latency Data Centers

100G/200G Electro-Optical Interfaces: The Future for Low Power, Low Latency Data Centers
by Kalar Rajendiran on 10-23-2023 at 6:00 am

112G Ethernet PHY IP EOE InterOp Demo JR5 0179

Electrical copper interconnects, once the backbone of data center networks, are facing growing challenges. Rapid expansion of AI and ML applications is driving a significant increase in cluster sizes within data centers, resulting in substantial demands for faster I/O capabilities. While the surge in I/O requirements is being addressed by faster SerDes PHY technologies, interconnects are facing scaling challenges from power consumption perspective. This coupled with the imperative to flatten networks to minimize latency is driving the trend to optical interconnects. Another reason for this shift is the ability of optical interconnects to reduce channel loss, thereby improving data transmission efficiency. Optical interconnects also address the rigidity and space limitations associated with copper cables, providing greater flexibility in designing and expanding data center architectures.

The Rise of Optical Interconnects

Optical data transfer over optical fiber with minimal loss (compared to copper cable) over longer distances has been in use for a long time. Optical interconnects are nothing new to the industry, but the current implementation approach uses traditional optical modules which consumes a lot of power. Consequently, there is a significant push to integrate optical components into semiconductor electronics. The goal is to enable faster data transmission over longer distances, at low latencies and reduced power consumption.

Silicon Photonics

Silicon photonics is a field that leverages the semiconductor manufacturing process to create optical components on silicon substrates. Integrating photonics on silicon offers numerous advantages but comes with its set of challenges. One major challenge is achieving efficient light generation, modulation and amplification on a silicon platform. Silicon, being an indirect bandgap material, is not suitable for generation of light. As a result, integration of direct bandgap materials is required, which can be complex and costly.  Silicon photonics fabrication processes can vary from one foundry to another, some allowing monolithic integration of electronics and photonics on the same chip, while the others requiring co-packaging of electronic and photonic chips. Overcoming these challenges is crucial for realizing the full potential of silicon photonics in data centers.

OpenLight’s Integrated Photonic Integrated Circuits (PICs)

OpenLight has developed a technology to heterogeneously integrate indium phosphate (InP) on to a standard silicon process flow and create highly integrated devices. OpenLight’s PICs represent a significant advancement in the field of optical communication technology. These integrated circuits bring together a multitude of optical components, such as lasers, modulators, detectors, and waveguides, onto a single chip, offering a compact and highly efficient solution for data transmission and photonics applications. OpenLight’s Integrated PICs are engineered to meet the increasing demand for high-speed data transfer, lower power consumption, and enhanced performance. By consolidating these optical elements into a single package, OpenLight’s Integrated PICs facilitate seamless integration with electronic circuits, enabling more efficient and cost-effective solutions for data centers.

Synopsys and OpenLight Collaboration

Synopsys and OpenLight have collaborated to develop 100G/200G electro-optical interfaces that enable low power, low latency data centers. This electro-optical interface offers pluggable direct drive or linear or non-retimed interfaces. It enables data centers to choose high-speed connectivity options that suit their specific performance and power efficiency requirements, fostering flexibility and scalability in their network architecture.

Demo of 100G Electro-Optical Interface with TDECQ of 1.46dB

At the 2023 European Conference on Optical Communication (ECOC), Synopsys demonstrated its 112G Ethernet PHY IP Electrical-Optical-Electrical (E-O-E) interoperability success with OpenLight’s PIC. The eye diagram showed a TDECQ of 1.46dB, which is excellent. TDECQ stands for “Total Differential Eye Closure Quaternary,” a parameter used in optical communication systems to assess the quality of the received signal. TDECQ quantifies the amount of signal distortion or closure of the eye diagram in a digital communication system.

As shown in the block diagram below, the host PHY is driving the optical engine directly, avoiding the use of secondary PHY and DSP in the module. This approach is called linear drive or direct optical drive and leads to a 25% to 35% reduction in power consumption over a traditional optical module approach.

OpenLight recently unveiled the test results for the 200G Electro-Absorption-Modulator (EAM). This is a significant milestone toward enabling a 200G direct optical drive soon.

The Path to Success with Co-Simulation

The intricate interplay between optics and electronics requires seamless coordination to ensure optimal performance. One of the essential steps in harnessing the full potential of optical interconnects and high-speed SerDes is co-simulation. In a recent webinar, Synopsys emphasized the importance of co-simulation between optics and electronics and highlighted the comprehensive tool suite it offers to its customers.

Synopsys’ Photonic IC Design Solution

The Photonic IC Design Solution provides a suite of powerful design and simulation tools tailored for photonic devices. Engineers can create, analyze, and fine-tune a wide array of photonic components and circuits, including waveguides, modulators, detectors, and switches, with precision and accuracy. Its extensive library of pre-designed photonic building blocks, significantly expedites the design process by reducing the need to construct components from scratch.

The Synopsys solution promotes co-design, enabling seamless integration between electronic and photonic components. This ensures that both the electrical and optical aspects of a system are optimized for enhanced overall performance. Advanced simulation capabilities, including wave-optics and electromagnetic simulations, empower engineers to predict and understand the behavior of photonic components under varying conditions. Designers can iteratively refine their designs based on specific performance parameters like bandwidth, power consumption, and signal-to-noise ratio.

Synopsys’ OptSim

OptSim is a cutting-edge photonic system and circuit simulator designed to address the unique challenges and complexities of modeling and simulating photonic devices and systems. The simulator offers sophisticated optical modeling capabilities, enabling engineers to accurately model the behavior of light in various optical components and systems. OptSim seamlessly integrates with Synopsys’ electronic design automation (EDA) tools, allowing for co-simulation between photonic and electronic circuits.

Summary

As the demand for higher bandwidth and innovative data center architectures continues to surge, optical links are emerging as a pivotal solution. By embracing optical interconnects and leveraging high-speed SerDes solutions, data centers can achieve higher bandwidth, lower latency, more power-efficient data centers. The collaboration between Synopsys and OpenLight is leading the way in transforming data centers by harnessing the power of optical links. The successful EOE demonstrations substantiate the robustness of these next-gen optical link solutions. The emergence of standards-compliant technologies like 112G LR, VSR, XSR/Direct-drive, and the next-generation 224G is poised to revolutionize optical links, making them the ideal choice for 800G/1.6T data transmission. Co-simulation between optics and electronics is the key to unlocking the full potential of this transformative technology. Synopsys equips designers with a comprehensive set of tools to seamlessly implement, analyze, and verify their optical link designs.

For more details,

visit www.synopsys.com/ethernet

visit www.synopsys.com/photonic-solutions/optsim.html

Also Read:

Qualcomm Insights into Unreachability Analysis

Synopsys Panel Updates on the State of Multi-Die Systems

Synopsys – TSMC Collaboration Unleashes Innovation for TSMC OIP Ecosystem


Podcast EP188: The New Demands for Memory Design and the Synopsys Approach with Anand Thiruvengadam

Podcast EP188: The New Demands for Memory Design and the Synopsys Approach with Anand Thiruvengadam
by Daniel Nenni on 10-20-2023 at 10:00 am

Dan is joined by Anand Thiruvengadam, director of product and business management and head of the Solutions and Go-to-Market functions for the memory market segment at Synopsys.

Anand discusses the substantial demands experienced by memory designers due to trends such as big data analytics. He describes how these demands impact the design flow both during the design phase as well as after tapeout, creating a full silicon lifecycle management requirement, New effects that must be modeled such as aging and radiation are also discussed.

Against this backdrop Anand outlines the full-stack approach Synopsys has taken to address these design challenges. The company-wide focus on memory design as well as the addition of new AI techniques are presented.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.


ASML- Longer Deeper Downcycle finally hits lithography – Flat 2024 – Weak Memory – Bottom?

ASML- Longer Deeper Downcycle finally hits lithography – Flat 2024 – Weak Memory – Bottom?
by Robert Maire on 10-20-2023 at 8:00 am

ASML Monopoly
  • ASML reports in-line QTR but future looks flat for 2024
  • Downcycle finally hits litho leader- ASML monopoly solid as ever
  • Memory remains bleak – New China sanctions unclear
  • Recovery timing is unclear but planning for an up 2025
In Line Quarter and year as expected

Overall revenues came in at Euro6.7B with EPS at Euro4.81, more or less in line with guidance and expectations. The company appears on track for its previously guided 30% growth in 2023 over 2022.

The obvious issue was that orders were down (-42%) significantly to Euro 2.6B with only Euro0.5B in EUV bookings which suggest weakness at leading edge and sustaining business at trailing technology.

Overall the company is looking at a flat 2024 over 2023……..

Length & Depth of downturn confirmed as it finally hits ASML

In the many years we have followed the semiconductor industry, it has always been the case that lithography tools were the last to be canceled/slowed while most other tools saw an immediate impact.

If the current downcycle were a year or less or limited to just the memory sector, its likely that ASML would have skated over the downcycle without impact while others got hit.

The length and depth of the current downturn is much deeper and longer than most previous cycles and thus has finally caught up with ASML. Customers are obviously less concerned about canceling and delaying orders as they are getting off the order queue that usually lasts well over a year. They are likely more confident that they will be able to get the tools whenever the recovery actually recovers.

This also seems to suggest that the recovery cycle will be longer and slower than prior recoveries otherwise customers would want to have equipment to be ready, and wouldn’t slow ASML orders.

A three or four year downcycle?

The downcycle started in the spring of 2022. If we assume that we are coming close to a bottom at the end of 2023 (as ASML suggests) we have spent the last year and nine months on the way down to the bottom.

If we assume a slow recovery (which already seems indicated) we won’t see a recovery back to prior levels until some time in 2025 (at best).

That would peg the current downcycle at 3 to 4 years making it one of the worst overall.

We were more negative than most every analyst going into the downturn and unfortunately we have been proven correct at the length and depth even though we had hoped to be wrong.

Monopoly remains solid

Despite recent hysteria and bad information there is no threat to ASML’s position on the horizon whatsoever.

The primary threat remains market health and demand. Sanctions are a secondary threat but less impactful than demand related issues.

China sanctions initially sound less impactful

Although ASML is still reading recently released sanctions from the US to figure out the impact, it appears at first blush that the impact is less than what could have otherwise been.

It looks like enough ARFi tools will be shipped into China to help out ASML’s revenues while “bad actors” in China will still be on the “verboten” list.

Final export licenses and approvals remain to be seen but so far “draconian” sanctions appear to be off the table.

Looks like Gina took the slap in the face and didn’t respond as much as could have been, showing restraint. Maybe Biden wants to have a better meeting with Xi.

High NA likely to be a bright spot in 2024

The roll out of High NA tools at the end of 2023 and going into 2024 is likely to be a significant portion of business and new orders when the industry does actually start to recover probably in 2025.

Importantly the company has not cut back on R&D or leading technology efforts as it represents the future of the company.

We think orders and revenues on High NA tools will be one of the things that elevates ASML out of the downturn faster than others in the industry.

At $400M or so a pop, it doesn’t take a lot of orders to add up to real money.

Timing of CHIPS Act & fab construction just sucks

Unfortunately the last thing you want to do in an oversupply based downcycle is build more capacity……

The CHIPS act aims to do just that…..All the new fabs announced in the US, if brought on line in the previously expected timeline would tank the industry again.

Its quite clear that delays TSMC Arizona, Intel and others are more due to the current oversupply/downcycle than any other issue.

We would expect at least a 2-3 year delay if not more, of many of these projects. Chip companies are simply not stupid enough to spend money on new capacity when they are already swimming in it.

This is obviously unfortunate as it delays the US reshoring effort and dependence on Asia remains without a reasonable solution…..

The Stock

As expected, a longer cycle that has impacted ASML’s 2024 will weigh down the stock as no growth in 2024 over 2023 is clearly disappointing.

However, the longer term remains strong. ASML’s position remains strong. Not much has changed about the overall dynamics of the semiconductor industry.

We do see collateral damage to other chip equipment stocks as the length of the downcycle impacts others more so than ASML.

We will likely hear more of that through the rest of earnings season….

Most other chip equipment makers will likely try to put a good face on it but the reality is that this is a longer than expected and worse downturn.

When even ASML catches a cold the rest of the equipment makers catch pneumonia….

About Semiconductor Advisors LLC

Semiconductor Advisors is an RIA (a Registered Investment Advisor),
specializing in technology companies with particular emphasis on semiconductor and semiconductor equipment companies.
We have been covering the space longer and been involved with more transactions than any other financial professional in the space.
We provide research, consulting and advisory services on strategic and financial matters to both industry participants as well as investors.
We offer expert, intelligent, balanced research and advice. Our opinions are very direct and honest and offer an unbiased view as compared to other sources.

Also Read:

ASML- Absolutely Solid Monopoly in Lithography- Ignoring hysteria & stupidity

SPIE- EUV & Photomask conference- Anticipating high NA- Mask Size Matters- China

Micron Chip & Memory Down Cycle – It Ain’t Over Til it’s Over Maybe Longer and Deeper


CEO Interview: Pat Brockett of Celera

CEO Interview: Pat Brockett of Celera
by Daniel Nenni on 10-20-2023 at 6:00 am

Pat Brockett

Pat Brockett is a veteran of the global semiconductor industry. He began his career in sales and marketing at Texas Instruments. After that, he was senior vice president of worldwide sales and marketing at National Semiconductor. Subsequently, he headed the analog division and is credited with turning it around.

Later, he was CEO of the venture-backed programmable analog startup, Summit Microelectronics. The company led the mobile industry for ultra-fast battery charging and was purchased by Qualcomm for $350M.

Pat has been a board member and advisor to companies such as SureCall and Moonshot Antibodies.  For the past four years he was also an advisor to Celera. Pat recently stepped into the CEO role at the company and hired Alberto Viviani, another analog semiconductor veteran as COO.

Tell us about your company
Celera is disrupting the analog IC business. Analog design automation really doesn’t exist. For example, it takes at least a year to get a custom analog chip to market. Celera combines proprietary AI algorithms with decades of analog design experience to deliver custom chips in four months or less. Celera also has a world-class supply chain ensuring our customers are delivered the highest quality, cost-competitive product.

What problems are you solving?
Digital chip design has seen an incredible improvement in automation and overall design productivity over the past 20 years. Sophisticated automation takes care of a lot of chip implementation. AI is accelerating the process even further, with generative AI approaches promising to take digital chip design to new levels of automation.

Analog chip design, on the other hand, is done today about the same way it was done 20 years ago. It’s a very manual process, requiring deep domain expertise at every step to ensure a successful result. This situation creates several significant hurdles. Systems are using many more sensors and high-speed communication networks than ever before. These additions drive up the analog content of the system. At the same time, the expert analog designers we have come to rely on are aging out and there are few newly minted analog design experts to backfill them.

It is against this “perfect storm” that Celera was born. Most of the members of the company worked together for decades doing analog chips. This team got tired of the labor-intensive nature of the process and decided to find a better way. That better way is Celera and its patented, AI-assisted algorithmic design flow. This is a fundamentally new approach to analog chip design that will finally break the log jam and make custom analog chips available to all.

What application areas are your strongest?
The Celera approach to analog and mixed signal design can be applied to many design problems. To kick off the process and introduce this revolutionary technology to the market, Celera is already delivering custom power management integrated circuits (PMICs).

What keeps your customers up at night?
It depends on the type of customer. For chip companies, the challenge is getting many products to market fast. Since the design process is manual and is dependent on scarce analog designer resources, the pace of product introduction is often slower than ideal.

Large OEMs have the resources to build their own custom analog chips, but these designs can take longer than the digital part of the system. So, analog design becomes the “long pole” in product development, and this can result in lost revenue due to a late product introduction.

Small to mid-size OEMs have a different problem. These companies simply don’t have the resources to build custom analog chips. Rather, they use off-the-shelf parts integrated on complex circuit boards. The result is a suboptimal form factor, power dissipation and cost.

What does the competitive landscape look like and how do you differentiate?
The existing landscape consists of captive analog design groups inside of large system OEMs and analog design teams at chip and ASIC suppliers.

Celera has a team that is at least equal to our competition. What differentiates Celera from every other analog chip company is our AI-driven technology which reduces design time from many months to a few weeks.

Celera’s approach will disrupt the analog chip industry.

What new features/technology are you working on?
The current Celera model is to use our patented technology with our experienced design team to deliver custom analog chips faster and more reliably than ever before.

The ultimate goal of the company is to release our patented design approach via the cloud to make custom analog chips available to all. Called ChipHUB, this technology will allow system designers to specify what kind of custom analog chip they need without the need to know how to design it. That task will be done by ChipHUB.

How do customers normally engage with your company?
You can reach out to us via our website here. We’ll take it from there.

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The Path to Chiplet Architecture

The Path to Chiplet Architecture
by Paul McLellan on 10-19-2023 at 10:00 am

The Path to Chiplet Architecture

If you have anything to do with the semiconductor industry, you already know that one of the hottest areas for both manufacturing and EDA are systems designed with advanced packaging, basically putting more than one die (aka chiplets) in the same package.

When 3D packaging was first introduced, there were not really any effective design tools. Obviously, each chiplet could be designed the same way as a chip would be, but it was not really possible to examine the entire design as a single system. But people managed to successfully product working designs.

Early in technology development, optimizing the pin layout for power, performance, and area take priority. High pin count ASICs/FPGAs get broken down into smaller blocks (IOs, Complex IPs, Cores, AMS blocks etc.) that are instanced many times and are integrated to form the complete floorplan of the ASIC/FPGA or chiplet. This is not only the case for ICs, but also for interposers and package substrates.

Xpedition Substrate Integrator

As designs get larger, doing all this by hand becomes less and less feasible. This is where Siemens EDA comes in with the Xpedition Substrate Integrator (xSI) IC package floor-planning and assembly tool for the design phase, and the Calibre 3DSTACK and nmDRC tools for verification.

The chiplets in a chiplet-based design have many constraints at this floorplan level. Obviously, the bumps on the chiplet need to align physically with the interposer (or interconnect bridge). Signals that leave one chiplet need to go somewhere, such as to another chiplet or out to the actual package pins, typically by way of solder balls. Clearly, this provides plenty of ways to potentially mess up.

Power Delivery Network

One specific challenge in a chiplet-based design is the power delivery network (PDN). Given that the voltage may be, say, 0.8V and the power of the system might be measured in hundreds of watts, the current involved can be hundreds of amps. Since there may be 100,000 bumps or more to carry this high current, the only practical approach is to parameterize things. Nobody is going to place 100,000 bumps by hand.

As a recent white paper from Siemens EDA, The smart path to chiplets using hierarchical device planning and pin regions, explains:

The primary power/ground domain is surprisingly simple. The region will have a specific pin pattern, pad stack definition, and a repeating signal assignment pattern (checkerboard or horizontal/vertical striped). A highly efficient way to represent this design structure is as a set of parameterized pin regions.

The white paper goes into a lot of detail on how this is accomplished, along with an example design.

Physical Design

Next is to take the soft design and rearchitect into actual chiplets. The design (shown above) is The Soft IP SoC bump interface generated using parameterized pin regions containing 112,029 pins with eight power/ground domains and supporting 4-HBM interfaces.

When a design is constructed using hierarchical building blocks to represent the die-to-die interfaces along with parameterized pins to represent power distribution networks and signal patterns, the path to rearchitecting the SoC into chiplets is clear. Starting with the soft IP SoC representation, after the pins are removed, the region geometries can be quickly modified into a chiplet configuration as shown below.

With a few more steps detailed in the white paper, here is the final design complete with the HBM (high-bandwidth memory) stacks:

Summary

Package designers need to employ all the available tools to address the significant device complexity and explosion in pin count in today’s IC packaging designs, especially when early design analysis clearly detects errors. While it may still be possible to generate an initial draft of an advanced IC package design using non-graphical IC package floor-planning flows, it simply would not be feasible to keep up with the changes required by early design analysis. Siemens EDA has a portfolio of design tools that work together to deliver a correct design.

Please download the full white paper, The smart path to chiplets using hierarchical device planning and pin regions, in which a real example of a multi-die HBM-based design is used to show how package designs of complex chiplet-based designs can be created quickly and efficiently, without errors. Perhaps more importantly, iterative updates can be done in mere minutes or even seconds because of effective use of hierarchy in the design.

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IEDM 2023 is Coming in December

IEDM 2023 is Coming in December
by Scotten Jones on 10-19-2023 at 6:00 am

IEDM 2023

Anyone who has read my previous IEDM articles will know I view it as one of the best conferences on semiconductor process technology. From the tutorials, short courses and the conference papers there are so many great opportunities to keep up to date on the latest developments. The following are the conference organizers’ announcements on the conference.

The 69th annual edition of the IEEE International Electron Devices Meeting (IEDM) will be held in San Francisco on Dec. 9-13.  The news release below our names gives details of the conference program, and here’s a list of some of the anticipated technical highlights.

2023 IEEE International Electron Devices Meeting to Highlight Advances in Critical Semiconductor Technologies with the Theme, “Devices for a Smart World Built Upon 60 Years of CMOS”

  • Four Focus Sessions on topics of intense research interest:
  • 3D Stacking for Next-Generation Logic & Memory by Wafer Bonding and Related Technologies
  • Logic, Package and System Technologies for Future Generative AI
  • Neuromorphic Computing for Smart Sensors
  • Sustainability in Semiconductor Device Technology and Manufacturing

SAN FRANCISCO, CA (October 2, 2023) – Since it began in 1955, the IEEE International Electron Devices Meeting (IEDM) has been where the world’s best and brightest electronics technologists go to learn about the latest breakthroughs in semiconductor and related technologies. That tradition continues this year, when the 69th annual IEEE IEDM conference takes place in-person December 9-13, 2023 at the Hilton San Francisco Union Square hotel, with online access to recorded content available afterward.

The 2023 IEDM technical program, supporting the theme, “Devices for a Smart World Built Upon 60 Years of CMOS,” will consist of more than 225 presentations plus a full slate of panels, Focus Sessions, Tutorials, Short Courses, a career luncheon, supplier exhibit and IEEE/EDS award presentations.

“The IEDM offers valuable insights into where the industry is headed, because the leading-edge work presented at the conference showcases major trends and paradigm shifts in key semiconductor technologies,” said Jungwoo Joh, IEDM 2023 Publicity Chair and Process Development Manager at Texas Instruments. “For example, this year many papers discuss ways to stack devices in 3D configurations. This is of course not new, but two things are especially noteworthy about this work. One is that it isn’t just happening with conventional logic and memory devices, but with sensors, power, neuromorphic and other devices as well. Also, many papers don’t describe futuristic laboratory studies, but rather specific hardware demonstrations that have generated solid results, opening pathways to commercial feasibility.”

“Finding the right materials and device configurations to develop transistors that will perform well with acceptable levels of reliability remains a key challenge,” said Kang-ill Seo, IEDM 2023 Publicity Vice Chair and Vice President, Semiconductor R&D, Samsung Semiconductor. “This year’s program shows that electrothermal considerations remain a key focus, particularly with attempts to add functionality to a chip’s interconnect, or wiring, which is fabricated using low-temperature processes.”

Here are details of the 2023 IEEE International Electron Devices Meeting:

Tutorial Sessions – Saturday, Dec. 9

The Saturday tutorial sessions on emerging technologies are presented by experts in the field to bridge the gap between textbook-level knowledge and leading-edge current research, and to introduce attendees to new fields of interest. There are three time slots, each with two tutorials running in parallel:

1:30 p.m. – 2:50 p.m.

  • Innovative Technology for Beyond 2 nm, Matthew Metz, Intel
  • CMOS+X: Functional Augmentation of CMOS for Next-Generation Electronics, Sayeef Salahuddin, UC-Berkeley

3:05 p.m. – 4:25 p.m.

  • Reliability Challenges of Emerging FET Devices, Jacopo Franco, Imec
  • Advanced Packaging and Heterogeneous Integration – Past, Present & Future, Madhavan Swaminathan, Penn State

4:40 p.m. – 6:00 p.m.

  • Synapses, Circuits, and Architectures for Analog In-Memory Computing-Based Deep Neural Network Inference Hardware Acceleration, Irem Boybat, IBM
  • Tools for Device Modeling: From SPICE to Scientific Machine Learning, Keno Fischer, JuliaHub

Short Courses – Sunday, Dec. 10

In contrast to the Tutorials, the full-day Short Courses are focused on a single technical topic. They offer the opportunity to learn about important areas and developments, and to network with global experts.

  • Transistor, Interconnect, and Chiplets for Next-Generation Low-Power & High-Performance Computing, organized by Yuri Y. Masuoka, Samsung
  • Advanced Technology Requirement for Edge Computing, Jie Deng, Qualcomm
  • Process Technology toward 1nm and Beyond, Tomonari Yamamoto, Tokyo Electron
  • Empowering Platform Technology with Future Semiconductor Device Innovation, Jaehun Jeong, Samsung
  • Future Power Delivery Process Architectures and Their Capability and Impact on Interconnect Scaling, Kevin Fischer, Intel
  • DTCO/STCO in the Era of Vertical Integration, YK Chong, ARM
  • Low Power SOC Design Trends/3D Integration/Packaging for Mobile Applications, Milind Shah, Google

 

  • The Future of Memory Technologies for High-Performance Memory and Computing, organized by Ki Il Moon, SK Hynix
  • High-Density and High-Performance Technologies for Future Memory, Koji Sakui, Unisantis Electronics Singapore/Tokyo Institute of Technology
  • Advanced Packaging Solutions for High Performance Memory and Compute, Jaesik Lee, SK Hynix
  • Analog In-Memory Computing for Deep Learning Inference, Abu Sebastian, IBM
  • The Next Generation of AI Architectures: The Role of Advanced Packaging Technologies in Enabling Heterogeneous Chiplets, Raja Swaminathan, AMD
  • Key Challenges and Directional Path of Memory Technology for AI and High-Performance Computing, Keith Kim, NVIDIA
  • Charge-Trapping Memories: From the Fundamental Device Physics to 3D Memory Architectures (3D NAND, 3D NOR, 3D DRAM) and Computing in Memory (CIM), Hang-Ting (Oliver) Lue, Macronix

Plenary Presentations – Monday, Dec. 11

  • Redefining Innovation: A Journey forward in the New Dimension Era, Siyoung Choi, President & GM, Samsung Foundry Business, Device Solutions Division
  • The Next Big Thing: Making Memory Magic and the Economics Beyond Moore’s Law, Thy Tran, Vice President of Global Frontend Procurement, Micron
  • Semiconductor Challenges in the 5G and 6G Technology Platforms, Björn Ekelund, Corporate Research Director, Ericsson

Evening Panel Session – Tuesday evening, Dec. 12

The IEDM evening panel session is an interactive forum where experts give their views on important industry topics, and audience participation is encouraged to foster an open exchange of ideas. This year’s panel will be moderated by Dan Hutcheson, Vice Chair at Tech Insights.

  • AI: Semiconductor Catalyst? Or Disrupter? Artificial Intelligence (AI) has long been a hot topic. In 2023 it became super-heated when large language models became readily available to the public. This year’s IEDM will not rehash what’s been dragged through media. Instead, it will bring together industry experts to have a conversation about how AI is changing the semiconductor industry and to ask them how they are using AI to transform their efforts. The topics will be wide-ranging, from how AI will drive demand for semiconductors, to how it’s changing design and manufacturing, and even to how it will change the jobs and careers of those working in it.

Luncheon – Tuesday, Dec. 12

There will be a career-focused luncheon featuring industry and scientific leaders talking about their personal experiences in the context of career growth. The discussion will be moderated by Jennifer Zhao,

President/CEO, asm OSRAM USA Inc. The speakers will be:

  • Ilesanmi Adesida, University Provost and Acting President, Nazarbayev University, Kazakhstan — Professor Ilesanmi Adesida is a scientist/engineer and an experienced administrator in both scientific and educational circles, with more than 350 peer-reviewed articles/250 presentations at international conferences.
  • Isabelle Ferain, Vice-President of Technology Development, GlobalFoundries — Dr. Ferain oversees GF’s technology development mission in its 300mm fabs in the US and Europe.

Vendor Exhibition/MRAM Poster Session/MRAM Global Innovation Forum

  • A vendor exhibition will be held once again.
  • A special poster session dedicated to MRAM (magnetoresistive RAM memory) will take place during the IEDM on Tuesday, Dec. 12 from 2:20 pm to 5:30 p.m., sponsored by the IEEE Magnetics Society.
  • Also sponsored by the IEEE Magnetics Society, the 15th MRAM Global Innovation Forum will be held in the same venue after the IEDM conference concludes, on Thursday, Dec. 14.

For registration and other information, visit www.ieee-iedm.org.

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