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Synopsys 224G SerDes IP’s Extensive Ecosystem Interoperability

Synopsys 224G SerDes IP’s Extensive Ecosystem Interoperability
by Kalar Rajendiran on 11-27-2023 at 6:00 am

Synopsys 224G SerDes IP InterOp Multiple Tradeshows

Hyperscale data centers are evolving rapidly to meet the demands of high-bandwidth, low-latency applications, ranging from AI and high-performance computing (HPC) to telecommunications and 4K video streaming. The increasing need for faster data transfer rates has prompted a scaling of Ethernet from 51Tb/s to 100Tb/s. Numerous suppliers are offering IP and components such switches, backplane connectors, pluggables, cable assemblies and other networking infrastructure elements. Extensive ecosystem interoperability is a must to build robust systems.

Synopsys 224G SerDes IP

The Synopsys 224G SerDes IP is designed to provide exceptional performance, power efficiency, and configurability, making it a versatile solution for a wide range of applications, including high-speed networking, data centers, and artificial intelligence. This IP is engineered to support multiple industry-standard protocols, enabling it to seamlessly interface with a variety of communication standards. Its compatibility with protocols such as PCIe (Peripheral Component Interconnect Express), Ethernet, and Common Electrical I/O (CEI), showcases the SerDes IP’s versatility across different applications. The 224G SerDes IP offers a high degree of configurability, allowing designers to tailor its parameters to specific system requirements. Functional demonstrations highlight how the IP can adapt to different data rates, channel lengths, and signal integrity conditions, showcasing its flexibility in meeting the unique needs of various applications.

What might not be as widely known is Synopsys SerDes IP’s remarkable interoperability within an extensive ecosystem.

Attention to Ecosystem Interoperability

Synopsys recognizes the diversity of the modern semiconductor ecosystem, with various vendors providing critical components such as switches, pluggables, and other networking infrastructure elements. Synopsys collaborates with industry partners in the development and validation of its silicon proof points. This collaborative approach ensures that the technology is not developed in isolation but is tested and refined in conjunction with the broader semiconductor ecosystem. Synopsys invests heavily in rigorous testing and validation procedures to ensure that its solutions work seamlessly in real-world scenarios. This involves comprehensive testing with components from various vendors to simulate diverse networking environments. It includes stress testing under challenging conditions, demonstrating the SerDes IP’s reliability and stability in real-world applications.

Extensive Ecosystem Interoperability Demonstrations

Synopsys 224G SerDes IP continues showcasing extensive ecosystem interoperability through multiple tradeshows

Synopsys has actively demonstrated the interoperability of its 224G and 112G SerDes solutions in various settings, establishing its commitment to creating technology that seamlessly integrates into diverse environments. Some notable demonstrations include those at the TSMC Symposium 2023, OIF & OFC 2023, ECOC 2022, DesignCon 2023 and other industry events.

ECOC 2023:

Synopsys showcased the performance of its 224G TX and RX with Keysight test equipment and their latest SW for key 224G TX and RX characterization parameters. OIF Interop demonstrations include its 224G RX equalizing a 224G C2M channel and 3rd party 224G SerDes TX, showcasing BER orders of magnitude better than IEEE or OIF 224G Spec is indicating.

TSMC Symposium 2023:

The demo highlighted interoperability between Synopsys 224G hardware, connectivity, mechanicals, signal integrity, and power integrity, demonstrating superior performance in real-time.

OIF & OFC 2023:

Synopsys demonstrated the interoperability of its 224G and 112G Ethernet PHY IP solutions. The demonstrations featured wide-open PAM4 eyes, very low jitter, and excellent linearity, underscoring the robustness of Synopsys’ SerDes technology.

DesignCon 2023:

This video clip shows seven demonstrations of the Synopsys 224G and 112G Ethernet PHY IP, and the Synopsys PCIe 6.0 IP interoperating with third-party channels and SerDes.

ECOC 2022:

Synopsys showcased the performance and interoperability of its 224G and 112G Ethernet PHY IP solutions at ECOC 2022. Demonstrations included the world’s first 224G Ethernet PHY IP interop with Keysight AWG and ISI channel.

Synopsys Commitment to Furthering SerDes Technology

Synopsys’ commitment to pushing the boundaries of high-speed serial interface technology is evident in its multiple silicon proof points across various data rates, including 56G, 112G and 224G to implement 400G and 800G data connectivity. By successfully implementing and validating their SerDes IP across different data rates, Synopsys has showcased the robustness and adaptability of its core technology. This not only instills confidence in the current implementations but also suggests that the technology is well-prepared for the challenges posed by the upcoming 1.6Tbps speeds.

For details about Synopsys 224G Ethernet IP, visit the product page.

Summary

Synopsys 224G Ethernet PHY IP showcasing 224Gbps TX PAM-4 eyes in TSMC N3E

Synopsys 224G Ethernet PHY IP is available to help streamline the transition to 1.6T ethernet data transfer rate. In addition to doubling 112G data rates, the Synopsys 224G Ethernet PHY IP consumes one-third less power (per bit) compared to its predecessor while optimizing network efficiency by reducing cable and switch counts in high-density data centers. Synopsys is the first company to demonstrate 224G Ethernet PHY IP.

By emphasizing multivendor interoperability at 224G, Synopsys has positioned itself as a key enabler of the global data center ecosystem. Its solutions seamlessly integrate with a multitude of components, contributing to the efficiency and reliability of high-speed networking infrastructure.

Also Read:

Synopsys Debuts RISC-V IP Product Families

A Fast Path to Better ARC PPA through Fusion Quickstart Implementation Kits and DSO.AI

100G/200G Electro-Optical Interfaces: The Future for Low Power, Low Latency Data Centers


Podcast EP195: A Tour of Mythc’s Unique Analog Computing Capabilities with Dave Fick

Podcast EP195: A Tour of Mythc’s Unique Analog Computing Capabilities with Dave Fick
by Daniel Nenni on 11-24-2023 at 10:00 am

Dan is joined by Dave Fick, co-founder and CEO of Mythic. Dave leads Mythic to bring groundbreaking analog computing to the AI inference market. With a PhD in Computer Science & Eng from Michigan, he brings a wealth of knowledge and expertise to the industry.

Dan explores Mythic’s unique analog computing capability with Dave. The tradeoffs between edge and cloud processing are discussed. Dave explains the benefits of Mythic’s approach for edge computing in many demanding AI applications. Speed, power density, cost, form factor, training efficiency and latency are all discussed, highlighting the substantial benefits of the Mythic approach.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.


CEO Interview: Dr. Meghali Chopra of Sandbox Semiconductor

CEO Interview: Dr. Meghali Chopra of Sandbox Semiconductor
by Daniel Nenni on 11-24-2023 at 6:00 am

MeghaliChopra highres cropped

Dr. Meghali Chopra is co-founder and CEO of SandBox Semiconductor. She is responsible for SandBox’s vision and strategy and oversees the development of SandBox’s software products and technologies. Dr. Chopra received her PhD in Chemical Engineering from the University of Texas at Austin where her research focused on computational algorithms for plasma process optimization. She has her B.S. with Honors in Chemical Engineering from Stanford University. Dr. Chopra is an industry expert with publications in leading peer-reviewed journals and patents in the areas of semiconductor processing and computational optimization.

Tell us about your company?
Founded in 2016, SandBox Semiconductor is a pioneer in developing AI-based software solutions to accelerate process development for semiconductor manufacturing. Our fully integrated, no-code AI tool suite gives process engineers the ability to build their own physics-based, AI-enabled models to solve challenges during process definition, ramp-up, and high-volume manufacturing.

Using SandBox’s physics-based models and machine learning tools, process engineers in the semiconductor industry can virtually simulate, predict, and measure process outcomes. Even with small sets of experimental data, SandBox’s tools can extract valuable insights and patterns, helping engineers to gain a deeper understanding of manufacturing processes and to make informed decisions about recipe adjustments. SandBox leverages expertise in numerical modeling, machine learning, and manufacturing optimization to develop its proprietary toolsets, which are used by the world’s leading chip manufacturers and semiconductor equipment suppliers.

What problems are you solving?
At SandBox, we reduce cycles of learning for next-generation advanced manufacturing technologies.  To optimize a recipe, a process engineer must specify a process window for tens of process conditions including pressure, temperature, and gas flow rates. Determining the best process conditions is so challenging that oftentimes a recipe will take over two years to develop, or worse, the chip is dropped from production because the cost of the process development becomes too expensive. This technology gap and cycle time is a significant barrier to the deployment of novel microelectronic devices and imposes a substantial economic burden on semiconductor manufacturers who must make significant R&D investments to stay afloat.

SandBox provides computational modeling software that accelerates process development and enables semiconductor manufacturers to reduce costs, get to market faster, and commercialize new processes not possible before.

What application areas are your strongest?
SandBox works on leading-edge logic and memory manufacturing processes. Our users are typically performing technology development or high-volume manufacturing recipe optimization. Our technologies have been used on a range of optimization applications including feature-level, die-to-die, across-wafer, chamber-to-chamber, and tool-to-tool.

What keeps your customers up at night?
The process engineers we work with must figure out how to optimize many process conditions to manufacture billions of features across the wafer with nano-scale precision and at high throughput.  These process engineers are extremely knowledgeable and arguably the single most important individuals within each of our semiconductor customers. Unfortunately, these process engineers are often over-worked as they must continually push the envelope in advancing to the next node.  We developed our tools with these process engineers in mind – our mission is to provide meaningful leverage to the process engineer as he or she works to enable manufacturers to bring new microelectronics to market faster.

What does the competitive landscape look like and how do you differentiate?
Our proprietary modeling pipeline enables users to make process predictions with a small number of experimental data points.  The competitive landscape for process engineer-focused computational modeling tools is very limited.  Many of our customers have internal modeling groups, but our observation is that most frequently our process engineering users rightfully rely on their expertise and intuition to drive critical changes in recipe development.  To that end, the most common recipe optimization approach is the process engineer’s intuition.  We seek to help these process engineers in their role, particularly as the advanced manufacturing nodes increasingly push the limits of physics and chemistry in conjunction with the process engineer’s demands in a 24-hour day.

What new features/technology are you working on?
SandBox recently released a new product for its technology suite called Weave™. Weave™ significantly improves metrology accuracy and precision by leveraging advanced machine learning capabilities to extract and analyze profiles from SEM and TEM data. Process development engineers can spend up to 20% of their time manually measuring SEM and TEM images. With Weave, process engineers minimize tedious manual tasks and increase metrology accuracy, resulting in more insights, quicker experimentation, and reduced costs during process definition, ramp-up, and high-volume manufacturing.  The introduction of Weave continues on our platform vision as we work to provide a comprehensive tool-suite to bring easy to use physics-based AI tools to market with the goal of enabling the process engineer.

How do customers normally engage with your company?
Customers can reach out to us at info@sandboxsemiconductor.com or through our website at www.sandboxsemiconductor.com.

Also Read:

CEO Interview: Dr. J Provine of Aligned Carbon

CEO Interview: Vincent Bligny of Aniah

Executive Interview: Tony Casassa, General Manager of METTLER TOLEDO THORNTON


Generative AI for Silicon Design – Article 4 (Hunt for Bugs)

Generative AI for Silicon Design – Article 4 (Hunt for Bugs)
by Anshul Jain on 11-23-2023 at 8:00 am

Generative AI for Silicon Design 4

In the complex world of silicon design, ensuring the accuracy and reliability of our designs is paramount. As our chips become more sophisticated, the process of bug hunting—identifying and rectifying errors in our designs—becomes even more critical. Generative AI has the potential to revolutionize the silicon design industry by enhancing our bug-hunting capabilities. How? Let us experiment!

Experiment 4: Hunt for Bugs

To demonstrate the efficacy of Generative AI in silicon design, I conducted an experiment with OpenAI’s GPT-4. We provided the system with a design specification (sourced from https://mathcircle.berkeley.edu/sites/default/files/archivedocs/2010_2011/contest/1011contestpdf/comp8.pdf) alongside an implementation of the design. The goal? To see if GenAI could identify any bugs.

Design Specification:

On a 5 × 5 chessboard, a king moves according to the following rules:
1. It can move one square at a time, horizontally, vertically, or diagonally.
2. It can move in each of the eight allowable directions at most three times in its entire route.

Design Implementation in Verilog:

module chess (
    input clk,
    input reset,
    input [2:0] direction,      // 0-7 to indicate the 8 directions
    input move_request,         // Input to request a move
    output reg [2:0] cur_x_pos, // X position of the king
    output reg [2:0] cur_y_pos, // Y position of the king
    output move_ack,            // Acknowledgement of the move
    output reg error            // Error when a move in a direction exceeds limit
);

    // Define the directions: 0-7
    // 0: Right
    // 1: Left
    // 2: Up
    // 3: Down
    // 4: UpRight
    // 5: UpLeft
    // 6: DownRight
    // 7: DownLeft
    
    reg [2:0] cur_moves_count[7:0]; // Array to hold move counts for each direction
    reg [2:0] nxt_moves_count[7:0]; // Array to hold move counts for each direction
    always @(posedge clk) begin
	for (int dir = 0; dir < 8; dir++) begin
            if (reset) cur_moves_count[dir] <= 3'd0;
	    else cur_moves_count[dir] <= nxt_moves_count[dir];
	end
    end

    reg [2:0] nxt_x_pos, nxt_y_pos;
    always @(posedge clk) begin
        if (reset) begin
            cur_x_pos <= 3'd0;
            cur_y_pos <= 3'd0;
	end
	else begin
	    cur_x_pos <= nxt_y_pos;
	    cur_y_pos <= nxt_y_pos;
	end
    end

    always @(*) begin
        nxt_x_pos = cur_x_pos;
        nxt_y_pos = cur_y_pos;
        nxt_moves_count = cur_moves_count;
	error = 1'b0;
        if (move_request) begin
            case (direction)
                3'b000: if (cur_x_pos < 3'd4 && cur_moves_count[0] < 3'd3) begin
                            nxt_x_pos = cur_x_pos + 1'b1;
                            nxt_moves_count[0] = cur_moves_count[0] + 1'b1;
                        end
			else error = 1;
                3'b001: if (cur_x_pos > 3'd0 && cur_moves_count[1] < 3'd3) begin
                            nxt_x_pos = cur_x_pos - 1'b1;
                            nxt_moves_count[1] = cur_moves_count[1] + 1'b1;
                        end
			else error = 1;
                3'b010: if (cur_y_pos < 3'd4 && cur_moves_count[2] < 3'd3) begin
                            nxt_y_pos = cur_y_pos + 1'b1;
                            nxt_moves_count[2] = cur_moves_count[2] + 1'b1;
                        end
			else error = 1;
                3'b011: if (cur_y_pos > 3'd0 && cur_moves_count[3] < 3'd3) begin
                            nxt_y_pos = cur_y_pos - 1'b1;
                            nxt_moves_count[3] = cur_moves_count[3] + 1'b1;
                        end
			else error = 1;
                3'b100: if (cur_x_pos < 3'd4 && cur_y_pos < 3'd4 && cur_moves_count[4] < 3'd3) begin
                            nxt_x_pos = cur_x_pos + 1'b1;
                            nxt_y_pos = cur_y_pos + 1'b1;
                            nxt_moves_count[4] = cur_moves_count[4] + 1'b1;
                        end
			else error = 1;
                3'b101: if (cur_x_pos > 3'd0 && cur_y_pos < 3'd4 && cur_moves_count[5] < 3'd3) begin
                            nxt_x_pos = cur_x_pos - 1'b1;
                            nxt_y_pos = cur_y_pos + 1'b1;
                            nxt_moves_count[5] = cur_moves_count[5] + 1'b1;
                        end
			else error = 1;
                3'b110: if (cur_x_pos < 3'd4 && cur_y_pos > 3'd0 && cur_moves_count[6] < 3'd3) begin
                            nxt_x_pos = cur_x_pos + 1'b1;
                            nxt_y_pos = cur_y_pos - 1'b1;
                            nxt_moves_count[6] = cur_moves_count[6] + 1'b1;
                        end
			else error = 1;
                3'b111: if (cur_x_pos > 3'd0 && cur_y_pos > 3'd0 && cur_moves_count[7] < 3'd3) begin
                            nxt_x_pos = cur_x_pos - 1'b1;
                            nxt_y_pos = cur_y_pos - 1'b1;
                            nxt_moves_count[7] = cur_moves_count[7] + 1'b1;
                        end
			else error = 1'b1;
            endcase
        end
    end

    assign move_ack = move_request && !error;
	
endmodule

Identify functional bugs present in the Verilog implementation, create a counterexample for each functional bug with detailed input scenario, design transitions and a comparison of actual outcome versus expected outcome as per design specification.

Following is the output from GenAI model:

1. Bug: Overwriting the cur_x_pos with cur_y_pos

else begin
	cur_x_pos <= nxt_y_pos;
	cur_y_pos <= nxt_y_pos;
end

This section will cause the current x position of the king (cur_x_pos) to always take the value of nxt_y_pos, which is incorrect.

Counterexample:

Input Scenario: Assume the king is at position (2,2) and the move_request is provided with direction = 3'b010 (Up).
Design Transition:
   Expected: cur_x_pos remains 2 and cur_y_pos becomes 3.
   Actual: Both cur_x_pos and cur_y_pos become 3.
Outcome:
   Expected Outcome: King moves to (2,3).
   Actual Outcome: King moves to (3,3).
2. Bug: cur_moves_count[] initialization to zero

if (reset) cur_moves_count[dir] <= 3'd0;

All directions' move counts are initialized to zero upon reset. However, the condition to check for maximum moves uses < 3'd3, meaning the king can move 4 times in each direction before an error is raised.

Counterexample:

Input Scenario: Assume the king is at position (0,0) and four consecutive move_requests are provided with direction = 3'b000 (Right).
Design Transition:
   Expected: After 3 moves to the right, the 4th move should trigger an error.
   Actual: King moves four times to the right without triggering an error.
Outcome:
   Expected Outcome: King moves to (3,0) and then error is triggered.
   Actual Outcome: King moves to (4,0) without an error.
3. Bug: Lack of Boundary Check
Although the code contains boundary checks for the movement of the king on the chessboard, it does not account for the possibility that adding or subtracting from the 3-bit values might result in roll-over errors. For instance, if cur_x_pos is 3'd7 (which shouldn't happen based on the current design, but might due to external influences or other design issues), subtracting 1 might result in 0 rather than an expected 6 due to bit roll-over.

Counterexample:
This might be a theoretical bug as the current design does not allow for such a scenario to happen. However, it's essential to consider this for robust design.

Recommendation: Boundary checks can be improved, and additional sanity checks can be added to ensure that the position of the king never goes outside the valid range.
Intriguing Observations
  1. Bug Identification: GenAI model pinpointed a specific discrepancy between the design specification and its implementation with a proper counterexample including the scenario, transitions and actual vs expected outcome analysis. This was indeed a genuine bug that needed rectification.
  2. False Negative: Like any tool, Generative AI is not infallible. It did highlight an issue which, upon closer inspection, turned out not to be a bug. This serves as a reminder that while AI can be a valuable assistant, human expertise and judgment remain crucial in the validation process.
  3. Enhancement Issue: Beyond just bug hunting, GenAI model also proposed an enhancement—a suggestion for improving the design that wasn’t necessarily fixing a bug but rather optimizing the design further. This unexpected benefit demonstrates how AI can not only help in finding mistakes but also in suggesting innovations.

Tomorrow’s Landscape – GenAI powered HDL Code Editors/Analyzers!

The implications of this experiment are profound. By integrating Generative AI tools into our HDL code development flow, we can:

  • Accelerate the bug-hunting process: Automating the initial stages of bug detection can reduce the man-hours spent in the debugging long simulation waveforms.
  • Reduce verification cost: With fewer bugs left for verification tools/engineers to find, verification closure can be achieved sooner, leading to cost savings in the long run.
In Conclusion

As the semiconductor industry continues to evolve, leveraging tools like Generative AI can give us an edge, ensuring that our designs are not only error-free but also pushing the boundaries of what’s possible. It is only a matter of time when co-pilots and plug-ins gain wide adoption across the industry.

Also Read:

Generative AI for Silicon Design – Article 3 (Simulate My Design)

Generative AI for Silicon Design – Article 2 (Debug My Waveform)

Generative AI for Silicon Design – Article 1 (Code My FSM)


Handling metastability during Clock Domain Crossing (CDC)

Handling metastability during Clock Domain Crossing (CDC)
by Daniel Payne on 11-22-2023 at 10:00 am

synchronizer min

SoC designs frequently have lots of different clock domains to help manage power more efficiently, however one side effect is that when the clock domains meet, i.e., in a Clock Domain Crossing (CDC), there’s the possibility of setup and hold time violations that can cause a flip-flop to become metastable. Synchronizer circuits are then employed to mitigate the metastability issue, although they add non-deterministic delays to the logic path. The challenge for an RTL simulator is to take these non-deterministic delays into account.

CDC Synchronizer with 2 DFF

Siemens EDA wrote a white paper about this topic, and I’ll cover the traditional models for metastability effects, along with the model inside Questa CDC-FX.

In the synchronizer example from above, metastability happens when signal S changes too close to the rising edge of rx_clk, and the output of R1 glitches towards a 1, but settles down to a 0 in hardware, while an RTL simulator shows R1 transitioning to a 1 much quicker. This hardware metastability from R1 then makes R2 switch one clock cycle later in hardware compared to the RTL simulator.

Metastability adds ext-cycle delay

With the same synchronizer example when signal S arrives slightly after the rising edge of rx_clk then the output of R1 follows it to a 1 in hardware, while the RTL simulator waits until the next clock cycle for R1 to reach a 1 value, an effect called bleed-through. In this case the hardware transitions one cycle before the RTL simulator for both R1 and R2 signals.

Metastability and bleed-through

Both the extra-cycle delay and bleed-through cases only occur whenthe two clock domains, rx_clk and tx_clk have rising edges very close to each other in time. An ideal RTL simulator will match silicon for extra-cycle and bleed-through cases when:

  • Violations of setup constraints cause simulator to add cycle delay
  • Violations of hold constraints cause simulator to subtract a cycle delay
  • CDC signals are modeled independently
  • Registers with the same boundaries of clock domains have the same metastability effects

The RTL simulator industry has used several modeling methods to account for metastability effects.

  • Clock jittering – random changes to timing of clock edge, globally or locally.
  • 3 DFF synchronizer model – three registers instead of two.
  • Propagation delay-based method – a random delay inserted before the synchronizer.

Pitfalls are shown for each of these modeling methods and their variations, which then leads to how the Questa CDC-FX method was developed to accurately simulate metastability effects.

CDC-FX circuit model

When the two clock edges – tx_clk, rx_clk, are closely aligned in time and signal S is changing, this circuit will pseudo-randomly invert S that gets loaded into register R1. This means that in RTL simulation the output is forced into R1:

Instance of an CDC-FX

Both of the metastability effects introduced – extra-cycle delay and bleed-through – are modeled by inverting the value of S that gets loaded into R1. This CDC-FX circuit model can be automatically applied to every register that samples CDC signals.

Only the CDC-FX method satisfies all criteria for RTL matching silicon timing results.

Metastability methods comparison

Siemens recommends a complete CDC verification flow where the designer first runs a static CDC re-convergence analysis to remove any suspected re-convergence in the RTL. With netlist analysis three things are generated that are then used in subsequent steps:

  • CDC assertions
  • Coverage monitors
  • Metastability effects injectors

Verification engineers then simulate tests as a second step using the CDC assertions and coverage monitors from step 1. Tests identified as being effective in step 2 are run with the metastability effects injectors enabled in step 3. The coverage monitors actually track activity at each bit of every CDC register, then provide statistics:

  • Metastable cycles
  • Delayed transitions
  • Advanced transitions
  • Inverted bits bitmap

If the design under test fails with metastability modeling in simulation, then the design must be debugged to identify the source of improperly re-converging CDC signals.

Summary

CDC verification for metastability effects is a necessary step for all designs using multiple clock domains. Siemens EDA has developed the Questa CDC-FX method to be complete and accurate, working on all CDC signals. The extra-cycle delay and bleed-through delay effects are injected so that RTL simulation matches silicon behavior.

Read the complete white paper online here.

Related Blogs

 


Predicting Stochastic Defectivity from Intel’s EUV Resist Electron Scattering Model

Predicting Stochastic Defectivity from Intel’s EUV Resist Electron Scattering Model
by Fred Chen on 11-22-2023 at 6:00 am

Predicting Stochastic Defectivity from Intel's EUV Resist Electron Scattering Model

The release and scattering of photoelectrons and secondary electrons in EUV resists has often been glossed over in most studies in EUV lithography, despite being a fundamental factor in the image formation. Fortunately, Intel has provided us with a laboriously simulated electron release and scattering model, using the GEANT4 Monte Carlo simulator toolkit [1]. The simulator is able to track and keep statistics on all photons and released photoelectrons and secondary electrons and their trajectories. Consequently, it is possible to obtain the probability density for a given scattering distance at a given electron energy. In the resists studied, there were certain electron energies within the covered 10-82eV range where it was especially easy to trace electron scattering distances. Figure 1 shows the double Gaussian fitted probability density function for a 60 eV electron in SnOx resist and a 75 eV electron in chemically amplified resist.

Figure 1. Probability density functions for electron scattering distance for a 75 eV electron in chemically amplified resist (CAR) and 60 eV electron in SnOx. 25 mJ/cm2 EUV dose to a 100 nm x 100 nm patch of resist 50 nm thick. Data points sourced from Figure 7 of Ref. [1].

It is possible to get the population fraction beyond a given electron scattering distance, using the weighted average cumulative distribution functions of the two Gaussians. For example, a population fraction of 1e-11 goes beyond 20 nm for the 75 eV electron in CAR or the 60 eV electron in SnOx. This large electron scattering distance is a source of blur. Blur aggravates the impact of stochastic dose fluctuations because the peaks and valleys of the image are partly flattened by blur. A blur of 20 nm substantially destroys a 50 nm pitch image (Figure 2), regardless of exposure threshold, i.e., exposed critical dimension (CD). Essentially, there is a defect floor. For the smaller exposed CD, there is mostly unexposed area within the exposed region. For the larger exposed CD, there are exposed spots in the unexposed region.

Figure 2. Stochastic defectivity with decreasing resist exposure threshold (wider exposed CD), going from left to right. Exposure conditions: 50 nm pitch, 20 nm blur, 30 mJ/cm2 absorbed, secondary electron quantum yield=8. Pixel size: 1 nm x nm. More details in Refs. [2].

A defect probability of 1e-11 corresponds to a 1000 nm2 defective area per cm2 area. Or it can also mean, for example, one missing contact out of 100 billion contacts. When the blur probability matches the defect probability as in this case, we get a measure of the stochastic defectivity. A higher probability for defect-inducing blur can occur for smaller blur values, and this would happen for a smaller pitch. For the blur to play much less of a role in aggravating stochastic defectivity, the pitch has to be substantially larger than the blur. This also has the simultaneous benefit of making the stochastic fluctuations less significant by having more absorbed photons (per nm) per pitch.

References

[1] P. Theofanis et al., “Modeling photo, electron, and chemical interactions in a model hafnium oxide nanocluster EUV photoresist,” Proc. SPIE 11323, 113230I (2020).

[2] F. Chen, “Modeling EUV Stochastic Defects With Secondary Electron Blur,” https://www.linkedin.com/pulse/modeling-euv-stochastic-defects-secondary-electron-blur-chen/ (2023); also F. Chen, “EUV Stochastic Defects from Secondary Electron Blur Increasing With Dose,” https://www.youtube.com/watch?v=Q169SHHRvXE&t=94s (2023).

This article first appeared in LinkedIn Pulse: Predicting Stochastic Density from Intel’s EUV Resist Electron Scatterning Model

Also Read:

The Significance of Point Spread Functions with Stochastic Behavior in Electron-Beam Lithography

Extension of DUV Multipatterning Toward 3nm

Stochastic Model for Acid Diffusion in DUV Chemically Amplified Resists


Navigating Edge AI Architectures: Power Efficiency, Performance, and Future-Proofing

Navigating Edge AI Architectures: Power Efficiency, Performance, and Future-Proofing
by Kalar Rajendiran on 11-21-2023 at 10:00 am

CEVA Comprehensive Edge AI Portfolio

The surge in Edge AI applications has propelled the need for architectures that balance performance, power efficiency, and flexibility. Architectural choices play a pivotal role in determining the success of AI processing at the edge, with trade-offs often necessary to meet the unique demands of diverse workloads. There are three pillars of common AI processing architectures and related hardware and software requirements.

The Three Pillars of Common AI Processing Architectures

Scalar processing architectures are specifically designed for tasks that involve user interface management and decision-making based on temporal data with non-intensive compute requirements. These architectures excel in quickly and sequentially processing tasks, making them ideal for applications where swift decision-making is crucial. However, the trade-offs come in the form of limited parallelism compared to other architectures. While they are efficient for certain types of tasks, the sequential nature may pose limitations in handling workloads that benefit from parallel processing capabilities.

Vector processing architectures center on performing operations simultaneously on multiple data elements, making them particularly suitable for signal processing followed by AI perception tasks. Their key characteristics include enhanced parallelism, enabling efficient handling of tasks involving vectors and arrays. This parallel processing capability makes them well-suited for tasks that benefit from simultaneous data manipulation. However, a trade-off exists as vector processing architectures may not be as suitable for tasks with irregular or unpredictable data patterns. Their strength lies in structured data processing, and they may face challenges in scenarios where data patterns are less predictable or follow irregular structures.

Tensor (Matrix) processing architectures are specifically tailored for the demands of deep learning tasks, excelling in handling complex matrix operations integral to applications such as image recognition, computer vision, and natural language processing. Their key characteristics lie in the efficient handling of tasks involving large matrices and neural networks, making them essential for processing intricate data structures common in advanced AI applications. However, the trade-offs come in the form of intensive computational requirements, posing challenges in terms of power consumption. While these architectures deliver unparalleled capabilities in processing sophisticated tasks, the computational intensity may require careful consideration, especially in edge computing scenarios with limited power resources.

Hardware and Software Aspects

In terms of hardware for AI processing, a diverse array of solutions emerges to cater to varying requirements. Processor units, notably specialized ones like Neural Processing Units (NPUs), take the spotlight for their ability in handling intricate tasks associated with deep learning. Digital Signal Processors (DSPs) play an indispensable role, particularly in tasks involving signal processing, ensuring efficient and precise manipulation of data. Hybrid solutions mark a convergence of strengths, combining scalar, vector, and tensor processing architectures to achieve unparalleled versatility. This amalgamation provides a comprehensive approach to handling a broad spectrum of AI workloads. Further enhancing adaptability, customizable configurations enable hardware to be tailored and optimized for specific applications, ensuring efficiency and performance in diverse computing environments.

In terms of software for AI processing, a robust ecosystem is indispensable, characterized by optimized libraries, flexible frameworks, and developer tools. Optimized libraries stand as the basis for efficiency, offering specialized software components meticulously crafted to enhance the performance of AI tasks. Flexible frameworks play a pivotal role by providing a supportive environment that accommodates a variety of AI models, ensuring adaptability to evolving requirements. Complementing these, developer tools serve as catalysts in the configuration, optimization, and overall development of AI applications. Together, these software components form a cohesive foundation, empowering developers to navigate the intricacies of AI processing with efficiency, adaptability, and streamlined development workflows.

CEVA’s Pioneering Solutions

CEVA’s offerings address the full spectrum of AI workloads and architectures and stand out in fulfilling the power, performance, latency, versatility and future-proofing requirements of various AI applications.

CEVA-BX

The flexibility of CEVA-BX processors is a distinctive feature, enabling them to be finely configured and optimized for specific applications, offering a tailored approach to diverse computational needs. Their versatility delivers a delicate equilibrium between performance and power efficiency. This balance positions CEVA-BX as a fitting solution across a broad spectrum of edge computing applications.

SensPro2

Its vector DSP architecture, characterized by high configurability and self-contained functionality, positions SensPro2 as a versatile solution for a variety of applications. Particularly notable is its proficiency in parallel processing, where it excels in high data bandwidth scenarios, making it adept at addressing communication and computer vision tasks. In processing AI workloads, SensPro2 showcases remarkable efficiency, seamlessly handling tasks with a throughput of up to 5 TOPS (Tera-Operations Per Second).

NeuPro-M

The versatility of NeuPro-M shines through as it adeptly handles a diverse spectrum of Advanced Neural Network models, showcasing its adaptability to the evolving landscape of AI applications. Its Neural Processing Unit (NPU) IP stands as a testament to CEVA’s commitment to low-power, high-efficiency processing, making NeuPro-M a frontrunner in energy-constrained scenarios. A noteworthy feature contributing to its future-proofing capabilities is the built-in VPU (Vector Processing Unit). This allows NeuPro-M to efficiently manage not only current but also emerging and more complex AI network layers, ensuring sustained relevance and optimal performance in the dynamic and rapidly advancing field of Edge AI.

Summary

In navigating the diverse landscape of Edge AI architectures, the choice between scalar, vector, and tensor processing architectures involves weighing trade-offs and aligning solutions with specific workload requirements.

CEVA’s pioneering solutions, including CEVA-BX, SensPro2, and NeuPro-M, stand out by providing a comprehensive suite that addresses the three pillars of common AI processing architectures. With a focus on flexibility, efficiency, and future-proofing, CEVA empowers developers and businesses to navigate the complexities of Edge AI, making intelligent architectural choices tailored to the evolving needs of the industry.

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Cadence Integrates Power Integrity Analysis and Fix into Design

Cadence Integrates Power Integrity Analysis and Fix into Design
by Bernard Murphy on 11-21-2023 at 6:00 am

Voltus Insight AI min

As integration levels increase, clock frequencies rise, and feature sizes shrink it is not surprising that all or most aspects of semiconductor design become more complex and demand more from design technologies. One example where the traditional approach is breaking down is in optimizing power distribution networks (PDNs) for electromigration and IR drop (EMIR). Historically designer have first run detailed EMIR analysis, then have implemented fixes to fold into the next design update, repeating periodically as implementation evolves. That method is no longer scaling effectively for very large designs at 7nm and below. To address this scaling problem Cadence has just announced a new AI-centric EMIR optimization tool supporting a combined analysis and fix in-design flow, following the path timing analysis took in earlier generations. They see this new approach to EMIR as an IR 2.0.

The problem statement

The trick in designing a PDN for a design is to ensure that metal routes are sufficiently low resistance, from the top level down through multiple metal layers to a gate that is switching. If resistance through that path is sufficiently high, that will result in a voltage drop below the nominal operating voltage causing the gate to switch more slowly than intended, therefore triggering unanticipated timing failures. Naturally other gates switching at the same time (aggressors) add to current demand in the same vicinity, further amplifying the voltage drop. In FinFET designs aggressors account for as much of the IR drop experienced by any given node. In effect, managing noise on the power network has become just like a signal integrity problem.

The IR 1.0 approach to the problem has been focused on analysis to find the hotspots, providing guidance to designers on what they need to fix. That has worked very well, but below 7nm resistance in the lower-level metal networks has become so significant that a victim in a block instance may have as many as 8-10k aggressors contributing up to 80% of the drop on the gate of immediate interest.

These compounded contributions complicate the analysis problem, but more important they create a deluge of IR drop violations (hundreds of thousands), making it impossible for a designer to fix any but a few of the most critical issues. Worse yet, in fixing one issue the designer has little insight into how an individual fix will impact timing for the other thousands of connected gates. The real goal should be to eliminate the great majority of violations without messing up PPA or DRC.

IR 2.0 with Voltus InsightAI

The only way to address the problem is to intelligently automate EMIR analysis/fixing together with PDN implementation, in the same we were forced to couple timing analysis and optimization with physically aware synthesis years ago. This is a perfect application for AI, not because a smart designer can’t figure out how to fix an individual IR drop problem or a problem coupled with a bit of surrounding complexity but because the sheer scale of coupled devices and interconnect has grown beyond human abilities to manage, no matter how skilled the engineer.

Voltus InsightAI uses a generative AI approach to develop and refine a power grid to minimize EMIR issues, maintain timing and power goals, while avoiding area overhead for an over-designed power grid. At the outset when reading in a design, the Learn capability creates AI models for the power grid, suitable for fast incremental IR drop analysis based on dynamic vector data. Discover runs root-cause analysis to prioritize large drops by finding aggressors and looks for resistance bottlenecks in the grid and power density hotspots.

Improve is a recommender technology which looks at many methods through which IR drop problems could be fixed and suggests optimal choices to address as many as violations as possible while honoring PPA and DRC constraints. The solution integrates through Empower with Innovus, Tempus, Voltus Power Integrity, and Pegasus in support of on-the-fly fix and check iterations.

In PDN design with Voltus InsightAI, designers use the tool first before signal routing. After signal routing has been inserted, they use the tool again to further refine optimization. Throughout the tool is self-training, updating after every few rounds of changes. No specialized pre-training is required.

All sounds good on paper; how does it deliver in practice? Several customers have been running trials, MediaTek among them. They have already provided an endorsement with hard numbers. They say they have seen a 65-70% reduction in IR drop violations at the block level, optimizing using both vectorless and vector-based flows. Not bad.

Very interesting stuff. You can learn more HERE.


Webinar: Silicon Catalyst & EE Times Examine the Bigger Picture Aspects of AI – Nov. 29, 2023 – 9am to 10am Pacific

Webinar: Silicon Catalyst & EE Times Examine the Bigger Picture Aspects of AI – Nov. 29, 2023 – 9am to 10am Pacific
by Mike Gianfagna on 11-20-2023 at 2:00 pm

Webinar Silicon Catalyst & EE Times Examine the Bigger Picture Aspects of AI – Nov. 29, 2023 – 9am to 10am Pacific

Artificial Intelligence (AI) is dominating the news cycle these days. It used to be about the latest (and largest) chips to accelerate AI algorithms. While that’s still relevant and exciting, AI news is taking a much broader, socioeconomic character. What does AI mean for job security, the economy, or even life on Earth? These aren’t hyperbolic comments. Just browse some recent headlines – OpenAI shakeup has rocked Silicon Valley, leaving some techies concerned about the future of AI, Biden signs executive order to promote ‘responsible innovation’ of AI,  Global Leaders Warn A.I. Could Cause ‘Catastrophic’ Harm. AI has become an important topic on the world stage. Recently, Silicon Catalyst assembled a group of technology executives to discuss what our “AI Wonderland” will look like. As an important follow-on to the 6th Annual Semiconductor Industry Forum, up next is a webinar hosted by Silicon Catalyst and EE Times to take a broader look at AI and its impact. Read on to understand how Silicon Catalyst & EE Times examine the bigger picture aspects of AI, beyond the technology innovation cycle.

Previous Live Event Recap

 

 

 

 

 

Silicon Catalyst hosted a well-attended live event at the SRI Conference Center in Menlo Park, CA on Thursday, November 9, 2023. Questions discussed at the event included:

  • What are the AI technologies that will create new business models and industries?
  • What are the implications to semiconductor industry success for incumbents & startups?
  • How do we address the power-hungry AI hyper-scalers’ impact on our energy resources?
  • What impact will potential government and industry regulations have on innovation?

You can read the pre-event coverage on SemiWiki here.  There is also an event replay link on the Silicon Catalyst website, The event was well attended and widely covered. The prestigious IEEE Spectrum covered the event . Part of that coverage included some memorable quotes from the panelists. Some of those deserve repeating here:

  • “If you don’t think of [AI] as a paradigm break or something that can put you out of business, you’re in trouble.” —Deirdre Hanford, Chief Security Officer, Synopsys
  • “AI can take analog libraries and move them from generation to generation [of technology] automatically; this used to be incredibly time consuming, error prone, and difficult.” – Moshe Gavrielov, former Xilinx CEO and now a member of both TSMC‘s and NXP’s board of directors
  • “We are entering an era of (AI-assisted) electronic design creation.” – Ivo Bolsens, Senior VP, AMD

The panelists also exhibited a sense of humor regarding the Alice in Wonderland theme for the event, as shown below.

[left to right] Richard Curtin, David French, Pete Rodriguez, Moshe Gavriolev, Deirdre Hanford, and Ivo Bolsens.

What’s Coming Next

Continuing the theme of the coming AI Wonderland, Silicon Catalyst is teaming up with EE Times for a live broadcast webinar on November 29, 2023 from 9:00 – 10:00 AM Pacific time. The webinar will be moderated by Nitin Dahad, EE Times Correspondent and will expand the conversation on AI to include topics such as:

  • Social Impact
  • Regulatory oversight
  • Investment strategies

The panelists for this webinar are high-profile individuals that span many areas touched by AI. They are:

Jama Adams, COO of Responsible Innovation Labs, www.rilabs.org  

Jama Adams

Jama Adams is COO of a coalition of leading startup founders and investors creating the next generation of high growth technology companies with responsible innovation at their core. Jama was the first hire on Bill & Melinda Gates and Warren Buffett’s Giving Pledge and took the pledge from zero to $1 trillion in three years, growing the ranks to nearly 100 billionaires (today it stands at $3 trillion from 236 signers). She raised $1.8 billion in Series B funding in 12 weeks for Commonwealth Fusion Systems. In other roles – as founder of a consulting firms, on the Omidyar impact investing team, as Communications Director for the City of New York, on political campaigns, on Capitol Hill, and at Harvard Kennedy School, Jama has brought together elite influencers, frontline organizers, business executives, and created new organizations and industries to make change.

Navin Chaddha, Managing Partner, Mayfield, www.mayfield.com  

Navin Chaddha

Under Navin’s leadership, Mayfield has raised eight U.S. funds and guided over 80 companies to positive outcomes. He has been named a Young Global Leader by the World Economic Forum and has ranked on the Forbes Midas List of Top 100 Tech Investors fifteen times, including being named in the Top Five in 2020, 2022 and 2023. Navin’s investments have created over $120 billion in equity value and over 40,000 jobs. During his venture capital career, Navin has invested in over 60 companies, of which 18 have gone public and 27 have been acquired. Navin holds an MS degree in electrical engineering from Stanford University and a B.Tech degree in electrical engineering from IIT Delhi, where he was honored with the distinguished IIT Alumni Award. Navin is an active philanthropist who supports education, diversity, equity, inclusion, and food scarcity groups.

Rohit Israni, Chair AI Standards, US (INCITS/ANSI), www.incits.org

Rohit Israni

Rohit is the founder and CEO of CertientAI. He is also the Chair AI Standards for the US national body responsible for developing US positions and contributions to international AI standards being developed by ISO/IEC (ISO/IEC JTC 1/SC 42). He is also the liaison for SC 42 with Organization of Economic Cooperation and Development (OECD). Prior to founding CertientAI, he led Intel’s global scale ecosystem enabling programs in the Developer Relations Division for AI, Datacenter and Network, of which he co-founded the AI partnership program (Intel AI Builders). Rohit earned a master’s degree in engineering with a specialization in Robotics and AI from Tulane University. He also holds a master’s degree in management science & engineering from Stanford University where he was a part of the Stanford Technology Ventures Program.

To Learn More

This is an impressive group of panelists and a must-see event. Registration information can be found at https://www.eventbrite.com/e/navigating-the-ai-wonderland-tickets-760825638967?aff=oddtdtcreator.  And that’s how Silicon Catalyst & EE Times examine the bigger picture aspects of AI on technology innovation and ultimately, on our lives.


China’s hoard of chip-making tools: national treasures or expensive spare parts?

China’s hoard of chip-making tools: national treasures or expensive spare parts?
by Craig Addison on 11-20-2023 at 10:00 am

Raiders of the Lost Ark warehouse photo courtesy Paramount Pictures
The Raiders of the Lost Ark warehouse. Photo courtesy Paramount Pictures.

In the closing scene of Steven Spielberg’s Raiders of the Lost Ark (1981), the camera pulls back to reveal an enormous warehouse stacked with crates of artifacts hidden away by the US government. 

One could imagine a similar warehouse in China today. The crates would hold a different kind of treasure – semiconductor production equipment.

Literally tons of foreign chip-making gear has been stockpiled by China in recent years – exceeding what is needed for current or even near-future production levels. That’s why ASML and Lam Research are reporting China sales reaching levels of 46 per cent and 48 per cent of total revenues, respectively, in the third quarter.

The biggest winner from this buying binge is Netherlands-based ASML. Even before the US government tightened export controls on chip-making tools to China, to include the Twinscan NXT1980Di, Chinese buyers were snapping up everything they could lay their hands on.  What’s more, the spending spree is bankrolled by China’s government through massive state subsidies that support local chip champions such as SMIC and YMTC.

Between January and August this year, China imported $3.2 billion worth of semiconductor manufacturing gear from the Netherlands, a 96.1 percent increase from the same period in 2022, according to figures cited in the 2023 Annual Report to Congress.

That’s pretty much all ASML. Do the math and it probably adds up to over 100 machines, given that most would not be high-end DUV systems costing 60 million euros (US$65 million) apiece. ASML has indicated that Chinese customers are buying mostly older machines, and they cost between 10 million and 20 million euros each.

China’s imports of semiconductor production equipment from all countries totaled $13.8 billion over the first eight months of 2023, according to the same report. This is by no means a recent trend. In 2020, Chinese chip makers spent almost $32 billion buying tools from suppliers in Japan, South Korea, Taiwan and elsewhere, a 20 per cent jump from 2019.

“China has already made the decision that it is going to buy all the equipment that it can possibly buy for as long as it can buy it,” said Gregory Allen, an AI and chip expert at the Washington-based think tank Center for Strategic and International Studies, speaking on the Stratechery podcast on October 26.

The Twinscan NXT1980Di system, a workhorse for many Chinese fabs, was introduced by the Dutch firm in 2015. Last week, at a major China trade expo in Shanghai, ASML China president Shen Bo told local media that by the end of this year the company’s installed base of “photolithography machines plus measurement machines” in China would be “close to 1,400”.

A few years ago, an ASML lithography system was even used by a wafer fab start-up in Wuhan, central China, to wrangle more than $2 billion in funding from the provincial government. Two weeks later, the machine was put up as collateral for a $80 million bank loan. That turned out to be a ponzi scheme, with the fab in question, Hongxin Semiconductor Manufacturing Co (HSMC), collapsing at the end of 2020 without producing a single wafer.

So far, China has not been able to get its hands on one of ASML’s EUV machines, which have been strictly forbidden all along. However, Chinese fabs like SMIC are proving adept at stretching their DUV kit to produce 7-nm chips, like the one in Huawei’s Mate 60 5G smartphone.

SMIC is accelerating its acquisition of fab tools. When announcing third quarter results last week, co-CEO Zhao Haijun said the company would ask suppliers to speed-up deliveries to “ensure ramp-up of production at plants that have been initiated”, due to the impact of geopolitics on shipment schedules. SMIC raised its annual capex budget to $7.5 billion for 2023, 18 per cent higher than last year.

What is the risk of China reverse engineering one of ASML’s top-end DUV immersion systems, thus insulating itself completely from export bans? Given enough time, anything is possible. That’s certainly the overarching goal of the Chinese state, according to experts.

“I have not heard of a machine that is currently in China that there is not a Chinese company working on reverse engineering,” Allen said on the Stratechery podcast. “China’s ability to reverse engineer a Lam etching tool in 2010 was pretty crummy. China’s ability to reverse engineer in 2023 has improved considerably… every single component is the same. The spare parts for our machines work as the spare parts for their machines,” he said.

That begs the question: what will China do with its stockpile of foreign semiconductor production equipment if it successfully transitions to locally made gear copied from the West? To be sure, they’ll be stuck with a big warehouse of (very expensive) spare parts.

Also Read:

The Significance of Point Spread Functions with Stochastic Behavior in Electron-Beam Lithography

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ASML- Longer Deeper Downcycle finally hits lithography – Flat 2024 – Weak Memory – Bottom?