At the ISS Conference in January, An Steegen EVP of Semiconductor Technology & Systems at imec gave a talk entitled “Patterning Options for Advanced Technology Nodes”. I was present for her talk and had the opportunity to have a follow up interview with An.
To open her talk An laid out the case for continued semiconductor scaling needs – the explosion of data traffic, increasing bandwidth needs and emerging IOT system of systems. An then moved into a discussion of dimensional scaling.
Dimensional scaling of semiconductors is under pressure, Logic, DRAM and NAND have all scaled to pitches too small to be printed in a single exposure by argon fluoride immersion lithography (ArFi) leading to multi-patterning and EUV. The complexity of lithography techniques is also driving the need for Design Technology Co-Optimization (DTCO) – more on this later.
For an IMEC N7 node with a 32nm metal pitch there are three options for patterning:
Working towards EUV An showed results from a 0.33 numerical aperture (NA) EUV tool achieving a 32nm pitch with a 34.5mj/cm2 dose (target <20mj/cm2) and line width roughness (LWR) of 4.5nm (target 3.2nm). A pitch of 26nm was also shown with a dose of 26mj/cm2 and a TBD LWR. See figure 1.
Figure 1. imec EUV single exposure results.
At imec work has been done with an Alpha demo tool from 2006 to 2011, the tool had a 0.25 NA and produced pitches from 80nm down to 54nm. From 2011 to 2015 an ASML NXE:3100 pre-production tool with a 0.25 NA was used to demonstrate pitches down to 36nm. The current tool introduced in 2014 has a 0.33 NA and has demonstrated pitches down to 26nm. Throughout this time improvements in photoresists, masks, CD control, throughput and overlay have all taken place in parallel.
Comparisons of EUV pattern fidelity to LE3 show much better fidelity and reduced variability. Designs can be more compact and produce better electrical performance, for example, superior via coverage has been shown. EUV can also reduce masks counts. See figure 2.
Figure 2. Mask count reduction with EUV.
The key focus areas for EUV readiness are:
- Increasing source power (towards 250W) and improving availability to >85% (>85%).
- Photoresist solutions that meet sensitivity and LER requirements simultaneously.
- Keeping masks defect free with pellicles and associated infrastructure.
- Mask yield and defect inspection/review infrastructure.
Currently most sources are running at 80 watts in the field, 125 watts is expected in the field at the end of 2016 and 250 watts has been demonstrated at ASML. Photoresists need to meet resolution, roughness and sensitivity requirements simultaneously and they are not there yet. There are also pattern collapse, etch resistance, contamination, and other concerns. Mask blank defects currently restrict EUV to dark field masks but during our follow up interview An noted that initial EUV insertion is planned for Via and block/cuts that are dark field masks anyway. In 2016 some companies began exploring EUV for metal patterns and they require lower mask blank defect levels and they are available but at lower yield and therefore higher costs. Metal-oxide photoresists are now comparable to chemically amplified resists but both resists need improvement for LWR at low dose. Roughness reduction strategies are being explored such as etch or deposition assisted smoothing as well as track vapor smoothing and directed self-assembly smoothing. See figure 3.
Figure 3. LWR reduction techniques
Despite a 10x per year reduction in added particles per pass, pellicles are still needed. Pellicles need to have >90% single pass EUV transmission, be mechanically stable and chemically stable while exposed to hydrogen and EUV. I specifically asked An whether pellicles would be ready in time for production in late 2018 or early 2019. olysilicon-based pellicle are a promising candidate for initial EUV insertion, but are unlikely to be viable above 250 watts At imec various pellicle material options such as coated carbon nanotubes are being developed and look promising for >250 watt use in the 2019 – 2020-time frame. Figure 4. presents some pellicle options.
Figure 4. EUV Pellicle options
Despite the progress described above, simple dimensional scaling will not provide 50% per node area reduction in the future and DTCO is needed.
The size of a standard cell is the contacted poly pitch (CPP) in one direction and the minimum metal pitch (MMP) multiplied by the number of tracks in the other direction (see figure 5).
Figure 5. 9 track standard cell with 4 fins per FET
Up to this point we have been discussing dimensional shrinks that reduce CPP and MMP but cell size can also be scaled by reducing the number of tracks. The challenge of this is that moving from a 9 track cell as shown with 4 fins for the nFET and 4 fins for the PFET to a 7.5 track cell, you can only fit 3 fins for the nFET and 3 fins for the pFET (see figure 6).
Figure 6. 7.5 track standard cell with 3 fins per FET
If no other optimization is done, reducing the fins per FET from 4 to 3 will reduce the drive current. There are however ways to mitigate the drive current reduction. One is to make the fins taller and try to get more drive current out of each fin. The other is to reduce parasitics that reduce performance. This is one place where reducing the number of fins makes things easier because the parasitics are generally reduced as the number of fins is reduced. This is an area where imec is doing a lot of work.
Authors note from Scott Jones: Based on my IC Knowledge data TSMC is believed to be reducing their minimum track height from 7.5-tracks at 10nm to 6-tracks at 7nm as part of their 10nm to 7nm density improvement. There is also some evidence that Intel may be going to a 5-track cell for their 10nm process, so DTCO is clearly being implemented in industry and not just an area of academic research.
Another area of research for continued scaling is the move to nanowires for improved electrostatics and shorter gate lengths. As I noted in a recent blog the minimum gate length for a FinFET is ~16nm and for a nanowire ~13nm. The shorter gate length enables tighter CPP to be achieved.
You can read my blog here.
In previous discussions An had discussed nanowires as being required for 5nm (imec N5). I asked her if with the foundries producing relaxed dimension 7nm processes whether the foundries might be able to produce a “foundry 5nm” technology with FinFETs and An agreed this might be possible. She did note that a transition from FinFETs to nanowires should provide at least a two-node solution to be attractive.
An touched on memory scaling in her talk and we discussed it further in our follow up interview.
In An’s presentation she presented pitches for D18, D14 and D10 DRAM nodes. I noted in our interview that my sense was that capacitor scaling had really hit a wall. That higher-k material had unacceptable leakage. An discussed double sided capacitors and work on the periphery for better sense amps to enable lower capacitance values to be used in the storage capacitor.
For 3D NAND An showed a roadmap: the goal for single stack 3D NAND is more than 64 layers. I found this very surprising with Intel-Micron going to a 2-stack process for their 64 layer part. imec has also been doing some very interesting work on higher mobility channel materials for 3D NAND. As the stack height grows the resistivity of the current polysilicon channels becomes an issue and imec has shown higher mobility InGaAS channels.
An concluded her talk with a discussion of functional partitioning of advanced SOC derives into multiple chips put together with 3D packaging.
In conclusion An laid out a vision of the future including EUV, DTCO with a transition to nanowires and heterogenous integration using 3D packaging.