WP_Term Object
    [term_id] => 1561
    [name] => ESD Alliance
    [slug] => esd-alliance
    [term_group] => 0
    [term_taxonomy_id] => 1561
    [taxonomy] => category
    [description] => 
    [parent] => 386
    [count] => 112
    [filter] => raw
    [cat_ID] => 1561
    [category_count] => 112
    [category_description] => 
    [cat_name] => ESD Alliance
    [category_nicename] => esd-alliance
    [category_parent] => 386

SEMICON West 2015 Recap – Day 1 – Softening Markets, Sub 14nm and 3D NAND

SEMICON West 2015 Recap – Day 1 – Softening Markets, Sub 14nm and 3D NAND
by Scotten Jones on 07-21-2015 at 6:00 pm

 Tuesday morning press briefing
The show started for me Tuesday morning with the SEMI press briefing. SEMI said there are 1,200 booths this year, 629 exhibiting companies and over 180 hours of programming. They also said pre-registration was up from last year and they expect 26,000 visitors.

Dan Tracy then gave an update on the markets.

Forecasts for the overall semiconductor market has been coming down as the year has progressed. Gartner just lowered their forecast to 2.2% and the average among forecasters is currently around 4%. The weakening euro and yen are holding down growth. The yen alone has accounted for a $600 million dollar reduction in semiconductor revenue year-to-date.

Silicon shipments year-to-date are up 8% versus growth last year of 11%. He thinks full year growth will be 5 to 6%.

Equipment billings are down 3.7% year-to-date but booking are up 3.7% so billing should rise later in the year. Memory is the big spender in 2015 and 2016 followed by foundry. Logic is generally flat for 2015 although some growth is expected in 2016. Overall the spending on equipment is expected to be $38, $40 and $42 billion dollars for 2014, 2015 and 2016 respectively. Foundries are ramping 200mm capacity in 2015 and 2016 driven by micro controllers, RF and power management.

Materials spending is expected to be $44, $46 and $48 billion dollars for 2014, 2015 and 2016 respectively.

Tuesday keynote panel on scaling the walls of sub-14nm manufacturing
The panel was moderated by Jo de Boeck of IMEC and included Mike Campbell of Qualcomm, Subhasish Mitra of Stanford University, Gary Patton of Global Foundries and Calvin Cheung of ASE.

Gary Patton (Global Foundries) was at IBM and with the Global Foundries (GF) acquisition has now moved into the CTO and head or R&D role at GF. He noted that he isn’t worried about physics but rather economics, he certainly seemed very confident and relaxed on the panel. He was bullish on GF’s new 22nm FDSOI process for IOT because it can be very power efficient running at 0.4 volts. Mobile is the big growth opportunity but is very cost sensitive. 10nm and 7nm will be more complex technologies, how to do that cost effectively is a big question. He thinks there are still orders of magnitude improvement opportunities, “we are still nowhere near where the human brain is”.

Mike Campbell (Qualcomm) noted that we need to look at end to end yield now including packaging and system yield. Sawing and packaging can change the IC performance. In the same vein he noted that foundries only want to provide PCM data but designers now need KLA data from the line. Silicon knowledge also needs to be transferred to packaging to help with yield ramps. “Semiconductors are a team sport now but everyone needs to speak the same language”. The tools all need the same data output without translators for greater interactivity. Tools for yield improvement need to be more predictive and interactive. In five years he wants 7nm technology with 28nm defect densities in high volume production. To get there we need to be more efficient.

Clavin Cheung (ASE) noted that die keep getting smaller while I/O is increasing and keeping it cost effective is a challenge. Yield needs to be monitored at each step though packaging. Mike Campbell interjected that there is no big yield company focused on packaging the way there is in the wafer fab.

Subhasich Mitra (Stamford) noted that development needs to take into account the entire system in order to optimize performance and power. A lot of bugs we see today are in power management functions embedded in the ICs. Bug fixes today are largely manual and take weeks or months, it needs to be automated and completed overnight. He thinks there is a 1000x energy efficiency opportunity still available.

I think to summarize the panel there is consensus that there is still a lot of room to produce more efficient – higher performance devices but it is getting harder and more collaboration is needed.

Tuesday afternoon TechSpot North Emerging Generation Memory Technology: Update on 3DNAND, MRAM and RRAM
Naga Chandrasekan of Micron provided Micron’s view of 3D NAND. Five years ago simple scaling ruled and there were many suppliers. Today there are few suppliers, many customers and simple scaling of 2D devices is no longer viable. Micron is focused 100% on 3D after the 16nm generation. Cost per Gb is lower for 3D than 2D. Scaling for 3D is limited by how high you can stack it and Micron thinks they can scale for at least 4 generations. There are a lot of process challenges around high aspect ratio deposition and etch, uniformity, hard mask materials, low temperature deposition, gap fill, stress and alignment. He thinks other emerging memories go into storage class memory but can’t displace NAND for storage because 3D NAND will still be the lowest cost.

Jim Handy of Objective Analysis noted that in the early nineties the switch from 1 or 4 bit DRAM to 8 or 16 bit DRAM stalled the introduction of new devices and again at 90nm DRAM stalled because nothing worked initially. He was skeptical that the introduction of 3D NAND would go smoothly.

Sanjeev Aggarwal of Everspin provided an update on MRAM. MRAM is a persistent RAM and combines the speed of RAM with non-volatility while providing better endurance than NAND. They view MRAM as high integrity non-volatile memory. The focus of Everspin engineering is on Spin Torque Transfer MRAM at 40nm and eventually 28nm to provide 1Gb + for PC applications. MRAM is manufactured in the top two metal layers of a CMOS process. 64Mb is currently in production on 90nm, it has 15ns access time with 10 year retention and better than 1E9 endurance. They are currently developing a 256Mb device – 40nm process on 300mm wafers at Global Foundries. They will then scale to 1Gb.

Robert Patti of Tezzaron gave an overview of the wide capabilities of Tezzaron. He thinks all processors will be 2.5D stacks in a few years. They take 28nm wafers from Global Foundries that are part way through the back end and fabricate things on top such as memory or MEMS. Tezzaron has a more than Moore fab to finish the processing.

From everything I have seen, I see 3D NAND as a huge hit over the next several years taking over from 2D NAND. For the other emerging memories they look like niche products to me.

Share this post via:


0 Replies to “SEMICON West 2015 Recap – Day 1 – Softening Markets, Sub 14nm and 3D NAND”

You must register or log in to view/post comments.