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TSMC 2026 OIP Ecosystem Forum Summary

TSMC 2026 OIP Ecosystem Forum Summary
by Daniel Nenni on 10-09-2026 at 8:00 am
Categories: Events, Semiconductor, TSMC

TSMC Ecosystem Forum Summary

TSMC’s 2026 Open Innovation Platform Forum presented artificial intelligence as the force reshaping semiconductor design. Its central argument is that faster chips will require progress across the whole system: logic, memory, packaging, interconnects, power delivery and design methods. TSMC places its partner ecosystem at the center of that work, describing collaboration as a way to turn increasingly complex technologies into chips customers can design and produce.

The keynotes began with the scale of OIP. Since its launch, the platform has expanded from design and intellectual property alliances into cloud, 3DFabric and AI-powered design collaborations. TSMC cites 28 trusted partners, more than 100,000 silicon-verified and production-proven IP offerings, and over 3,000 engineers with expertise spanning concept through silicon. Its IP portfolio covers building blocks such as memory, processors, interfaces, sensors and security across mobile, AI and high-performance computing, automotive and consumer applications. The message is that customers need dependable components and validated design flows as much as they need an advanced manufacturing process.

AI is also changing the kinds of systems customers want to build. TSMC pointed to applications including robotaxis, humanoid robotics and augmented or virtual reality, alongside growing demand for advanced-node silicon. Yet scaling AI creates linked challenges. Computing needs are rising rapidly, while memory capacity, data movement and power consumption constrain what systems can deliver. TSMC frames this as an opportunity for optimization across the stack, extending beyond the transistor to the package and the data center. The charts illustrate TSMC’s outlook and estimates; their forecasts should be read as projections.

For logic, TSMC emphasizes continuing improvements in power efficiency through process enhancements, design-technology co-optimization and circuit design. The deck argues that different workloads need different cell choices: high-performance CPUs and GPUs can prioritize speed, while more compact designs can use high-density cells to balance area and power. This reflects a broader theme of tailoring technology to the intended workload, particularly when energy use limits AI deployment.

Advanced packaging is another major focus. TSMC says its 5.5-times-reticle CoWoS package is in production and describes a path toward packages larger than 14 reticles, supported by the 3DFabric Alliance. Larger packages can bring logic and high-bandwidth memory closer together, but the deck also looks beyond today’s common configurations. As more AI work shifts from training toward inference and agentic applications, TSMC expects demand for memory choices optimized for bandwidth, latency and power. It illustrates options including 3D-stacked SRAM, high-bandwidth memory and DRAM integrated with logic. These options call for cooperation among electronic-design-automation providers, IP suppliers, memory companies, assembly and test firms, and substrate makers.

Connectivity receives its own roadmap. TSMC says a 200-gigabit-per-second micro-ring modulator using its COUPE technology is in production. It reports a bit-error rate below 10⁻⁸ and outlines further work on 400-gigabit-per-second modulation, multiple wavelengths and fiber-array integration, with a target of four terabits per second per millimeter by 2030. The point is that greater processing and memory capacity must be matched by ways to move data efficiently.

TSMC then turned to AI as a tool for designing AI hardware. TSMC describes methods extending from AI-based design-technology co-optimization through implementation and signoff. TSMC says more than 70% of OIP forum papers either use AI solutions or address AI use cases, and introduces six startups in an “Emerging Technologies Alley.” It’s proposed AI Design Kit, or ADK, shifts the design-enablement model toward an agentic AI framework that incorporates design information and training material. The vision is to improve models and flows, raise productivity and shorten the time needed to develop the next generation of chips.

Bottom line: TSMC expands the design boundary to the system level. The deck names COUPE, integrated voltage regulation, capacitors and thermal design-technology co-optimization as technologies relevant from AI chips through data centers. It calls for closer collaboration with original design manufacturers on shared design and analysis methods. Taken together, the slides present OIP as a means of coordinating specialized partners around a common problem: making future AI systems faster, more capable and more power efficient while keeping their design and production practical.

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From Cloud to Silicon: IC-Link and TSMC Open the Door

Beyond the Die: Verifying the Connected Chip

TSMC OIP Ecosystem Forum 2026: Spotlight on Emerging Technologies

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From Cloud to Silicon: IC-Link and TSMC Open the Door

From Cloud to Silicon: IC-Link and TSMC Open the Door
by Daniel Nenni on 10-07-2026 at 8:00 am
Categories: Chiplet, Semiconductor, TSMC

From Cloud to Silicon IC Link and TSMC Open the Door
From Cloud to Silicon: IC-Link and TSMC Open the Door

Access to advanced semiconductor technology involves much more than choosing a process node. Design teams also need computing capacity, compatible tools, secure technology access, and experienced support. IC-Link by imec’s expanded collaboration with TSMC addresses that combination, potentially making sophisticated chip development more practical for organizations that cannot build every capability internally.

Announced last month at the 2026 TSMC OIP Forum, the expansion brings IC-Link into TSMC’s Open Innovation Platform Cloud Alliance. According to imec, IC-Link will become the first managed cloud service supporting mixed-partner EDA flows for silicon design. Customers receive controlled access to advanced TSMC process design kits and scalable computing resources, while retaining their preferred tool chains and licenses. IC-Link manages secure hosting, infrastructure, and access to design resources.

That flexibility is particularly interesting. A chip design organization may already have substantial investment in its tools, workflows, and engineering expertise. Allowing those choices to carry into a managed environment could make adoption easier. My interpretation is that the offering’s value lies in combining infrastructure support with continuity for the customer’s established design practices.

Consider a hypothetical startup developing a specialized accelerator. Its engineers might have a compelling architecture and the necessary EDA licenses, but limited capacity to administer a demanding computing environment. A managed service could reduce the infrastructure work competing with design work. That would let the team spend more attention on its product, while drawing on external expertise where needed.

The relationship also has considerable history. IC-Link has belonged to TSMC’s Design Center Alliance since 2007 and Value Chain Alliance since 2009. The cloud initiative therefore extends an existing collaboration rather than establishing an entirely new route between the organizations. That background matters because customers need support that connects design decisions with the requirements of eventual manufacturing.

There is also an important packaging connection. In May 2026, IC-Link joined TSMC’s 3DFabric Alliance, which supports adoption of advanced packaging and silicon stacking technologies including CoWoS, InFO, and SoIC. Imec described that membership as strengthening IC-Link’s advanced integration capabilities and giving customers access to packaging expertise and a smoother path toward industrialization.

Taken together, these developments suggest a broader strategy: make more of the semiconductor development process accessible through a coordinated service relationship. The cloud announcement addresses the design environment, while the packaging alliance strengthens support for integrating components into complete systems. For customers considering chiplets, that combination could become increasingly useful as decisions about silicon and packaging become closely connected.

IC-Link’s wider service portfolio provides additional context. Imec describes offerings spanning technology selection, design and intellectual property, packaging, testing, qualification, and supply chain management. Customers can choose services that complement internal capabilities or pursue a full turnkey approach. The organization also supports integrated photonics and other specialized technologies, reflecting a remit that extends beyond conventional digital ASIC development.

Why does this matter? In my opinion, semiconductor competitiveness increasingly depends on how effectively a team can turn an idea into manufacturable hardware. Excellent architecture alone cannot resolve every implementation challenge. Services that reduce the operational burden around development could help more organizations attempt ambitious designs and make better use of scarce engineering resources.

For Europe, the potential significance is particularly clear. A stronger connection between research organizations, emerging chip companies, and commercial manufacturing could help translate technical expertise into products. That is a plausible benefit of the collaboration, rather than evidence that the announcement has already produced measurable regional growth.

For a prospective customer, the key question is whether this support removes enough setup and coordination work to improve the team’s ability to deliver a competitive chip on its intended schedule.

Bottom line: The practical results will depend on execution. Imec’s announcement does not quantify pricing, customer savings, or development time reductions, and it does not enumerate the nodes available through the cloud service. Those details will shape adoption. Still, the direction is meaningful: combining technology access, flexible design infrastructure, and expert assistance offers customers a more supported route from semiconductor concept to silicon.

Reference

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Beyond the Die: Verifying the Connected Chip

TSMC OIP Ecosystem Forum 2026: Spotlight on Emerging Technologies

TSMC’s AI Design Kit: Bringing Agentic AI Into Chip Design

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Beyond the Die: Verifying the Connected Chip

Beyond the Die: Verifying the Connected Chip
by Daniel Nenni on 10-06-2026 at 10:00 am
Categories: 3D IC, EDA, Events, Semiconductor, Siemens EDA, TSMC

Efficient, Scalable Methodology for Reliability and ESD Verification of Complex 3D IC CoWoS Systems
Efficient, Scalable Methodology for Reliability and ESD Verification of Complex 3D IC CoWoS Systems

One of the standout presentations at the 2026 TSMC OIP Forum highlighted a collaboration between Siemens EDA, Marvell, and TSMC. I always appreciate EDA presentations that bring together customer and foundry perspectives, and this one did not disappoint. We follow 3D IC technology closely and have published more than 150 blogs on the topic over the past three years. As chiplet adoption accelerates, I fully expect SemiWiki to publish twice that many over the next three, absolutely.

Advanced packaging is changing what it means to verify a chip. As semiconductor designers assemble multiple dies into increasingly complex systems, reliability can no longer be established by checking each component independently. The presentation, “Efficient, Scalable Methodology for Reliability and ESD Verification of Complex 3D IC CoWoS Systems” describes how Marvell and Siemens are addressing that challenge through automated verification of the complete assembly.

The shift reflects a broader change in semiconductor architecture. Instead of placing every function on one large die, designers can distribute functions across smaller dies, selecting technologies suited to each task. TSMC’s Chip on Wafer on Substrate, or CoWoS, technology supports this approach. The potential benefits include improved performance, lower power consumption, better manufacturing economics, and greater flexibility in combining different technologies.

But dividing a design creates new dependencies. Electrical connections now extend through dies, bumps, interposers, and substrates. A component that passes its own verification checks may still participate in an unsafe protection path once assembled with other components. The essential question becomes whether the entire system works together under the conditions its protection circuitry must withstand.

Electrostatic discharge, or ESD, illustrates the problem. Protection structures must provide suitable paths for discharge current, with sufficiently low resistance and adequate current carrying capacity. In a multidie assembly, the structure protecting a vulnerable circuit may reside on another die. Different dies can also have different protection schemes, manufacturing processes, and ESD requirements. Their individual qualifications therefore cannot substitute for checking the assembled protection network.

The methodology presented combines individual die verification with system level analysis. Each die is first checked using Siemens Calibre PERC and applicable foundry rule decks. Assembly information then supports Calibre 3D PERC checks across the integrated system. This preserves the value of established die verification while extending analysis to the connections and interactions introduced by advanced packaging.

Three areas receive particular attention: protection topology, point to point resistance, and current density. Topology checks establish whether required protection structures exist and connect as intended. Resistance checks assess whether discharge paths meet specified limits. Current density analysis evaluates whether the interconnect can carry the required current without exceeding its allowable capacity. Together, these checks address both the organization of the protection network and the physical adequacy of its paths.

Scale makes automation essential. One package ball can connect through multiple bumps and branches, producing many possible paths to analyze. Including substrate, interposer, and die contributions increases computational complexity. Engineers also need debugging tools that identify which layers or connections contribute to a violation, so they can locate the cause and make an informed design change.

The speakers describe an earlier workflow involving separate die checks, manual interface verification, and manual debugging that could take two to three weeks. Their automated approach brings die and assembly information into a holistic verification flow. The transcript does not provide a measured replacement runtime, but it clearly identifies the objective: reduce manual effort and improve the consistency of complex system checks.

Why this matters extends beyond verification productivity. AI infrastructure depends on powerful compute systems and the high bandwidth connections that allow accelerators to cooperate. Advanced packaging helps enable those systems, but integration also concentrates value and risk within each assembly. A protection failure can compromise a package containing multiple otherwise functional dies.

The presentation’s hypothetical yield example makes that exposure tangible. If ten components each have a 99 percent success probability, their combined probability is roughly 90 percent, assuming independent outcomes. This illustrates compounding risk, rather than predicting manufacturing yield. It reinforces the need to catch integration problems early. Finding those problems before fabrication can also prevent costly redesigns and protect schedules for products with demanding requirements.

Bottom line: The broader lesson is organizational as well as technical: reliability and ESD specialists should participate from the beginning. Effective verification requires rules matched to the assembly, clear protection requirements, and visibility across component boundaries. As chips become systems, verification must follow.

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Siemens and TSMC push AI deeper into chip design

From Custom Silicon to AI Systems: Why Cross-Layer Engineering Matters

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TSMC OIP Ecosystem Forum 2026: Spotlight on Emerging Technologies

TSMC OIP Ecosystem Forum 2026: Spotlight on Emerging Technologies
by Mike Gianfagna on 10-02-2026 at 8:00 am
Categories: 3D IC, Agentrys, AI, ChipAgents AI, EDA, Events, Semiconductor, Silimate, TSMC, Vinci

TSMC OIP 2026 Emerging Technologies Alley

The TSMC OIP Ecosystem Forum highlighted many accomplishments across TSMC’s vast ecosystem. Specific achievements with TSMC as well as collaborative work across several companies were all on display.

And there was an exhibit area where you could meet the companies behind many of these stories and learn more about them.

This year, there was a new area on the exhibit floor. TSMC invited six emerging companies to showcase their accomplishments. Called Emerging Technologies Alley, this new area on the show floor highlighted what these companies were doing to advance the state of design.

I had an opportunity to speak with all six. What follows is a short version of their story. There were five design technology companies and one IP company. Listed alphabetically, here is what I learned at the TSMC OIP Ecosystem Forum 2026 as the spotlight was focused on emerging technologies.

Agentrys

I spoke with Mark Ren (on the right) and Duo Ding (on the left). Agentrys is a tool builder vs. a tool provider. The company provides its customers with the ability to develop multi-agent frameworks that target their specific requirements.

Agentrys also provides “out of the box” solutions that can be used directly to address challenges such as design verification, root cause analysis, and RTL generation.

Agentrys didn’t just talk about these capabilities. They also ran several live demos to showcase out-of-the-box solutions as well as demos to show how to build your own multi-agent framework. Particularly difficult problems around SerDes integration were also addressed.

Overall, there was a lot going on at the Agentrys kiosk. Agentic design flows are on the rise. There are many offerings that harness this technology. What is unique about Agentrys is the company’s ability to provide out-of-the-box solutions as well as a development platform to allow customers to build their own custom agentic flows that continue to learn and get better with every design.

ChipAgents

I spoke with William Wang. William explained that ChipAgents is working with TSMC customers to jointly define the next generation of the spec to GDS agentic flow. He told me that ChipAgents is currently working with over 200 customers, so the company has a broad view of what is needed.

As a side comment, the growth of ChipAgent’s customer base is nothing short of spectacular. William pointed to the importance of working with TSMC to harness the power of its technology and vast ecosystem.

The knowledge that ChipAgents has gained from its extensive work with customers positions the company to work in a collaborative way with TSMC to more clearly define and deploy the next generation flow.

It will be interesting to watch the interactions between ChipAgents and the rest of the ecosystem including TSMC, as agentic design becomes more prevalent. ChipAgents has the qualities to lead the way.

INPSY

Inspy was the lone IP provider at Emerging Technologies Alley. This was also the first time the company exhibited at this show. Inspy focuses on IP to facilitate high-speed communication.

The company is a leader in ONFI (Open NAND Flash Interface) IP solutions. The Inspy ONFI PHY is a silicon-proven, high-performance physical layer IP solution that is purpose-built for the most demanding NAND Flash memory applications.

Inspy also provides broad support for high-speed die-to-die communications with libraries of both PHY and Controllers for UCIe 3.0.

UCIe-S delivers balanced performance and power efficiency for MCM packages. UCIe-A delivers leading bandwidth density for advanced packages, such as CoWoS, InFO, and EMIB. And UCIe-3D provides the ultimate density for next-generation 3D stacking. F2F, F2B, B2B, and multi-stack configurations are all supported.

Inspy is about seven years old. The broad support for applications including AI, HPC, data center, edge, automotive, and chiplet designs are good examples of why they were part of Emerging Technologies Alley.

Ricursive Intelligence

I spoke with Yi-Chen Lu. Ricursive Intelligence (spelled with “Ri” on purpose) offers an end-to-end, AI native chip design service. The company serves those customers that have a product vision that includes a custom chip, but doesn’t have the required team to get the job done.

Ricursive Intelligence provides performance architects to work with customer to design and deliver the critical custom chip. Capabilities include formal verification, and a very fast implementation flow. The company can go from RTL to GDS in minutes.

This flow includes many innovative, fast and accurate tools that Ricursive built from the ground up. Large customers have used some of these tools and found that they deliver superior results. The flow is AI native, so there has been significant training from the start in semiconductor design. The customer’s design data is also added to these models to make them specific to a particular customer’s needs.

The only customer that can be mentioned at present is Nvidia. Nvidia has an advanced hardware design team, but they use Ricursive Intelligence technology to extent their productivity. That is quite an endorsement for the Ricursive Intelligence flow. If you need an advanced chip designed, this organization is one to contact.

Silimate

I spoke with Ann Wu. Silimate has a large footprint for agentic chip design. At the TSMC OIP event the company focused on optimizing PPA using TSMC technology – helping digital design teams tape out PPA optimized chips faster.

From a bigger picture point of view, Silimate offers a complete system solution that ingests customer collateral and improves results autonomously. The tools blend with the customer’s existing flows and models to deliver superior results very fast.

Many of Silimate’s customers stopped by the kiosk during the event. The company seems to be building strong momentum across many applications and markets.

The offer to “converge to your PPA targets and fix functional bugs in days instead of months” is quite compelling. Silimate is a company to watch. I understand why TSMC chose to offer this organization a spot in the Emerging Technologies Alley.

Vinci

I spoke with Satish Radhakrishnan (on the left) and Hardik Kabaria (on the right). Vinci delivers a physics AI foundation model that natively understands the governing laws of physical systems. It combines AI acceleration with FEA solver accuracy to deliver full manufacturing-resolution simulations — without approximations.

It was pointed out that physics problems and the manifestation of thermal and thermal-mechanical problems are linked to performance, manufacturing, and advanced packaging. Growing design complexity is demanding that all these related issues must be addressed holistically, and problems must be detected early.

This is the only way to avoid the nightmare of discovering something like package warpage weeks before product introduction. This is the domain of Vinci, and a close relationship with TSMC will help to ensure manufacturing and advanced packaging dynamics are well understood.

One way to think about the impact of Vinci is to realize that one can now take multiphysics analysis and “shift left” to find problems much earlier, when they are easier to fix. After my conversation at the Vinci kiosk, I realized something else. Call it “the art of the possible.” By shifting accurate multiphysics analysis earlier in the design flow, it is now possible to not just optimize the current approach, but to also find a better approach. And that has significant implications.

To Learn More

I have just scratched the surface on what these six companies offer. If you want to dig deeper, the company website is great place to start. Many of these companies are also covered on SemiWiki, so I’ve included those links as well.

Agentrys website

Agentrys on SemiWiki

ChipAgents website

ChipAgents on SemiWiki

INPSY website

Ricursive Intelligence website

Silimate website

Silimate on SemiWiki

Vinci website

Vinci on SemiWiki

And that’s how the TSMC OIP Ecosystem Forum 2026 provided a spotlight on emerging technologies.

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TSMC’s AI Design Kit: Bringing Agentic AI Into Chip Design

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Why Advanced Chip Packaging Is Becoming a Design Problem

 

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TSMC’s AI Design Kit: Bringing Agentic AI Into Chip Design

TSMC’s AI Design Kit: Bringing Agentic AI Into Chip Design
by Daniel Nenni on 10-01-2026 at 10:00 am
Categories: AI, Events, Semiconductor, TSMC

TSMC’s AI Design Kit Bringing Agentic AI Into Chip Design

TSMC is introducing an AI Design Kit, or ADK, to help artificial intelligence tools make better use of its semiconductor manufacturing knowledge. The idea is to give AI agents that run chip-design workflows a technology-specific foundation, so they can adjust designs toward performance, power and area targets with less manual iteration. Announced in the context of TSMC’s Open Innovation Platform ecosystem event last week, the ADK points to a shift from AI assisting with isolated design steps toward agents coordinating more of the process.

A conventional process design kit, or PDK, contains the models, rules and files needed to design a chip for a particular fabrication process. TSMC’s ADK serves a different role. According to Aveek Sarkar, a TSMC director responsible for ecosystem and alliance management, it provides a “technology knowledge layer” for agentic design frameworks. In practical terms, an AI-driven tool could draw on that layer as it selects settings, evaluates tradeoffs and repeats electronic-design-automation tasks. TSMC has not publicly described the full contents, interfaces or licensing terms of the kit.

Why is such a layer useful? Chipmakers can start with validated reference flows, but those flows cannot prescribe the best settings for every circuit and product. A team designing an AI accelerator, for example, may prioritize speed and dense integration, while another customer values low power or cost. Engineers typically adjust tools and examine the consequences for timing, energy use and physical layout. At advanced process nodes, these choices interact in complicated ways. A faster feedback loop can make it easier to explore options before a design is finalized for fabrication, a milestone known as tape-out.

TSMC says its ADK will enable agentic AI tools and workflows built on knowledge specific to its technologies. An agent might run a design tool, inspect the result, change parameters and run it again, using measured outcomes to decide what to try next. This is an illustration of the intended workflow, not a published specification of ADK functions. TSMC expects the approach to speed circuit- and architecture-specific optimization and plans to develop it with partners that supply electronic design automation software.

The company has cited productivity gains of three to five times for digital design and up to six times for analog and radio-frequency design in discussing the initiative. Those are TSMC’s stated figures; its public explanation does not give enough detail to treat them as a universal performance benchmark. Results would depend on the design task, the software involved, the starting point and how productivity is measured. The ADK’s value will become clearer as customers and partners describe actual deployments and comparable outcomes.

The project fits within TSMC’s broader Open Innovation Platform, which connects its manufacturing technologies with design tools, intellectual property, cloud services and specialist partners. TSMC has already worked with partners on AI-based design tools and has used reinforcement learning for circuit optimization and design-space exploration. The ADK is intended to help agentic systems use that ecosystem more effectively. At its 2026 ecosystem forum, TSMC highlighted AI-driven automation tools and agentic workflows as ways to handle growing design complexity.

There are limits to what an agent can settle on its own. A design that appears better on one metric may create problems elsewhere, including timing, heat or manufacturability. For multi-die systems, the interactions between chips, packaging and interconnects add further constraints. Engineers still need reliable models, verification and sign-off before a design can be manufactured. TSMC describes the ADK as a way to guide optimization within design workflows, not as a substitute for those checks.

Bottom line: The ADK is best understood as an emerging layer between TSMC’s process expertise and AI-driven design software. If it works as intended, it could shorten the cycle between a design decision and trustworthy feedback. The unanswered questions are concrete: which tools will use it, how much of the workflow agents can control, what information the kit supplies, and whether the claimed gains hold across customer designs.

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TSMC OIP Ecosystem Forum 2026: Broadcom’s View of ASICs and Ecosystems

TSMC OIP Ecosystem Forum 2026: Broadcom’s View of ASICs and Ecosystems
by Mike Gianfagna on 09-30-2026 at 12:00 pm
Categories: 3D IC, AI, Events, Semiconductor, TSMC

TSMC OIP Ecosystem Forum 2026 Broadcom’s View of ASICs and Ecosystems

I spent a significant part of my career in the ASIC business. This segment of semiconductors has always been challenging, difficult and invigorating. There is something special about delivering a working custom chip that enables your customer to bring a world-changing product to market. It has always been a highly competitive business. For many years, I recall Broadcom being the one to beat. The combination of a vast library of proven IP from its broad product portfolio (especially its SerDes) and the deep design skills that came from the LSI Logic acquisition made the company hard to beat.

At this year’s TSMC OIP Ecosystem Forum, Broadcom took the stage for the second keynote address of the event. I found it fascinating to get a close look at what makes the Broadcom ASIC engine tick. There were some familiar topics around superior IP and design methodology, but there were also some new items of interest. The way Broadcom works with the larger ecosystem, especially TSMC described an important margin of victory. Let’s look closer to better understand Broadcom’s view of ASICs and ecosystems at TSMC OIP 2026.

Solving Today’s XPU Challenges with Tomorrow’s Solutions

Greg Dix

That was the general topic of this keynote, presented by Greg Dix, Vice President of Engineering, ASICs Product Division at Broadcom. Greg painted a diverse and colorful picture of the ASIC business and what it takes to win in such a demanding market.

He touched on many topics, including IP, process, materials, integration and methodology. What was most interesting to me is how Broadcom views the broader ecosystem. Relationships with companies such as TSMC play an important role in its market dominance.

Here are some of the key points offered by Greg during his keynote.

As AI chips become larger, faster, and vastly more complex, Broadcom is betting that the winners will be those who solve tomorrow’s engineering problems before customers even encounter them.

The race to build the next generation of AI computing is no longer simply about making a faster chip.

It is about integrating enormous amounts of compute, memory, connectivity, and packaging into systems so complex that many of the technologies needed to build them must be invented years before the final product reaches the drawing board.

That was the central message of Broadcom’s keynote –

“Roadmap the Future: Solving Today’s XPU Challenges with Tomorrow’s Solutions”

The company’s view is straightforward: in custom silicon, winning the next major XPU program requires more than delivering today’s technology. It requires anticipating what customers will need several generations from now—and having those capabilities ready when the opportunity arrives.

That challenge is especially important in the ASIC market.

Unlike a general-purpose processor where customers largely accept a predetermined set of features, performance targets, and design tradeoffs, an ASIC starts with the customer’s workload and objectives. The customer determines what it wants; Broadcom’s task is to assemble the right mix of process technology, IP, memory, connectivity, packaging, and design methodology to make that vision possible.

That flexibility is powerful, but it dramatically raises the stakes.

New semiconductor technologies often require two or three years to develop and qualify. By the time a customer needs an advanced capability, it may already be too late to begin developing it. Broadcom therefore places multiple technology bets in parallel, evaluates them aggressively, and abandons approaches that fail to deliver sufficient value.

The objective is not merely to win a design. It is to become what Greg described as an “enduring incumbent”—a partner customers return to because previous commitments were delivered. A supplier can win once by promising an aggressive schedule, technology, or price. Winning repeatedly requires something harder, execution.

That pressure has fundamentally changed Broadcom’s approach to technology adoption. In earlier semiconductor generations, the company could wait until a process was mature, models were stable, and manufacturing risks were understood. AI accelerators no longer permit that luxury. Broadcom has moved from being a fast follower to an early adopter, working with partners such as TSMC while technologies are still evolving.

The advantage is not simply speed. Early adopters can help shape emerging technologies around the needs of future products. Nowhere is that evolution more visible than in advanced packaging.

AI processors have expanded from large monolithic dies connected to conventional memory into sophisticated assemblies containing multiple compute dies, I/O chiplets, high-bandwidth memory, interposers, and increasingly, vertically stacked silicon. Instead of placing every function on the most advanced—and most expensive—process node, designers can disaggregate the system and place different functions on the technologies best suited to them.

Broadcom sees 3D integration as the next major step.

Stacking dies introduces an entirely new set of engineering problems: delivering power through multiple layers of silicon, extracting heat from stacked structures, performing timing analysis across dies manufactured on different process nodes, testing individual components before expensive assembly, and managing an enormous increase in design compute requirements.

The solution is to address these problems before the customer design begins.

Greg described an extensive program of mechanical, thermal, electrical, and risk-mitigation test vehicles intended to validate new technologies ahead of production. These platforms allow engineers to study everything from package warpage and thermal behavior to SerDes performance, HBM operation, routing, and system-level integration.

The goal is what Greg repeatedly called “first-time-right” silicon.

For today’s largest AI accelerators, a silicon re-spin can mean far more than an engineering delay. It can mean missing the market entirely.

That reality is also reshaping design methodology. Broadcom expects development to become increasingly concurrent: process technology, packaging, IP, design tools, and customer products evolving at the same time rather than sequentially.

Artificial intelligence itself will accelerate that transformation. Broadcom expects AI-driven design techniques to compress implementation schedules even further, placing increasing pressure on backend design, verification, compute infrastructure, and methodology.

Greg pointed to a recent large XPU program that moved from kickoff to tapeout in roughly nine months—an illustration of how quickly expectations are changing.

Yet perhaps Greg’s most important message was not about any individual technology.

It was about collaboration.

Future XPUs cannot be designed in isolation. Success will depend on semiconductor companies working closely with foundries, memory suppliers, packaging houses, EDA vendors, equipment providers, and customers—often while the underlying technologies themselves are still being developed.

Greg explained that Broadcom’s philosophy is that “hard problems are a good thing.”

He pointed out there will be plenty of them ahead. AI systems will demand more compute, more memory bandwidth, larger packages, faster interconnects, improved thermal solutions, and increasingly sophisticated integration.

For semiconductor companies, those challenges create risk—but they also create differentiation.

And in Broadcom’s view, the companies that solve those problems before the market needs the answers will be the ones positioned to win the next generation of AI silicon.

To Learn More

Greg’s keynote touched on many key trends and market requirements, but the complete story is much larger. You can explore a larger view of Broadcom’s capabilities here. And that’s Broadcom’s view of ASICs and ecosystems at TSMC OIP 2026.

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Why Advanced Chip Packaging Is Becoming a Design Problem

Siemens and TSMC push AI deeper into chip design

TSMC OIP Ecosystem Forum 2026: Opening Remarks

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Why Advanced Chip Packaging Is Becoming a Design Problem

Why Advanced Chip Packaging Is Becoming a Design Problem
by Daniel Nenni on 09-29-2026 at 2:00 pm
Categories: 3D IC, EDA, Semiconductor, Synopsys, TSMC

Why Advanced Chip Packaging Is Becoming a Design Problem

Addressing Inter-Die Complexity for 3D Multi-Die Design by Synopsys / Arm

As chipmakers put more computing power into a single system, the challenge extends beyond making individual chips faster. They must connect multiple chips, memory stacks, power supplies, and sometimes optical components in a compact package. In the2026 TSMC OIP Forum talk “Addressing Inter-Die Complexity for 3D Multi-Die Design by Synopsys / Arm”, TSMC describes how that growing complexity is changing the tools used to design chips. Physical layout, electrical performance, heat, and mechanical structure now have to be considered together.

The first challenge is integration. Modern packages can place chiplets side by side and stack them vertically. Connections that pass through silicon, wiring tracks, and the spaces available for standard cells all follow different grids. If those grids are poorly aligned, a connection may block more usable space than necessary. TSMC describes adjusting connection placement to recover space for circuit cells. A small percentage gain can matter when repeated across a large design: it creates room for useful circuitry without requiring a new manufacturing process.

Chiplet placement presents a related problem. Moving one component can force several others to move because of spacing, enclosure, and symmetry rules. The speaker describes work with electronic design automation partners to express those rules in forms that placement software can act on. The talk also describes an AI system that examines remaining rule violations and proposes fixes. In one example, it resolves a spacing violation by changing which edges line up, rather than simply pushing two chiplets farther apart. The practical benefit is less manual rework as packages become more crowded.

The second challenge is high speed communication. Closely packed connections can interfere with one another, weakening signals even when every wire satisfies manufacturing rules. TSMC’s approach is to translate signal quality requirements into routing instructions that software can follow, including shielding and consistent connection shapes. The speaker reports that automated tools routed large groups of signals in minutes where manual work would take much longer. These are results reported in the talk, not a guarantee that every design will see the same improvement. They show why routing software must consider electrical behavior while it lays out wires.

Checking those connections is difficult too. A designer may need to estimate how often a transmitted bit will be read incorrectly, including errors so rare that direct simulation takes too long. The talk describes a statistical method intended to make those checks practical. Faster checks let engineers test more design choices before committing to a layout.

The third challenge is power and heat. More computation in a smaller area demands more power. Sending that power as high current wastes energy and generates heat in the package’s electrical paths. TSMC describes placing voltage conversion closer to the computing chips so power can travel farther at a higher voltage and lower current. That can reduce losses, but it adds components that must be modeled. The speaker says simplified, layered models have reduced simulations that once took more than a month to a matter of days.

Heat also becomes harder to predict as chip structures and materials change. A model that spreads heat evenly across a circuit cell can miss hot spots near its active parts. The talk describes more detailed thermal models for new power structures, metal wiring, and optical components. Accurate temperature estimates are especially important when optical behavior changes with heat.

Finally, the speaker emphasizes design readiness. A promising packaging technology is only useful if engineers have reliable rules, models, and software to design with it. TSMC says it has tested these materials with tool partners and found issues involving capacity, runtime, and accuracy. That work may sound less dramatic than a new chip architecture, but it determines whether customers can build complex products predictably.

Bottom line: Progress in computing increasingly depends on making many components work as one system. Better placement preserves scarce space; better routing supports faster communication; better power delivery limits wasted energy; and better models reveal problems before fabrication. The talk’s central message is that advanced packaging needs an equally advanced design process. As systems grow denser, gains will come from coordinating manufacturing technology and design tools across the whole package.

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Siemens and TSMC push AI deeper into chip design

Siemens and TSMC push AI deeper into chip design
by Daniel Nenni on 09-29-2026 at 8:00 am
Categories: AI, EDA, Semiconductor, Siemens EDA, TSMC

Siemens and TSMC push AI deeper into chip design

Siemens and TSMC are expanding their collaboration on semiconductor design tools, with a focus on AI assisted workflows, advanced chip packaging and support for newer manufacturing processes. Their announcement centers on an AI agent intended to find and fix design rule violations: errors that can prevent a chip layout from being manufactured as planned.

The proposed workflow connects Siemens’ Calibre verification software with its Aprisa and Solido design tools. Instead of requiring engineers to diagnose every violation and make each correction by hand, the agent is designed to identify a problem, analyze its context, suggest or carry out a fix, and check the result. Siemens and TSMC say this could reduce manual work and shorten the path to tapeout, when a finished design is sent for manufacturing.

That is a meaningful target. Modern chips contain enormous numbers of features, and each new manufacturing process comes with detailed rules governing how those features can be placed and connected. A design may work in a simulation yet still fail a manufacturing check. Fixing one violation can also create another or affect power use, speed or chip area. Verification is therefore an iterative part of development, not a box engineers tick at the end.

The companies describe a broader ambition for Siemens’ Fuse EDA AI system: agents that can work through long, multistep tasks across several tools and validate their own outputs. The collaboration also covers custom chip design and the placement and routing of digital circuits. The practical question is how reliably these systems can handle real projects, where an apparently simple correction may have consequences elsewhere in the design. The announcement describes capabilities and expected benefits, but does not provide customer results showing how much time or cost they save.

The work extends beyond AI. Siemens says its tools support several TSMC process technologies and aspects of TSMC’s 3DFabric packaging platform. In 3D designs, engineers may stack chips or connect separate pieces of silicon, often called chiplets, within one package. Those choices introduce challenges involving connections between chips, signal quality and heat. Siemens reports expanded verification support for stacked designs, thermal analysis work and continuing development of chip and package design flows. Some capabilities have been certified for particular TSMC technologies; others remain under development or certification.

Why it matters

Chip design is becoming a coordination problem as much as a drawing problem. Engineers must balance performance, energy use, manufacturability, reliability and heat, often across multiple pieces of silicon. Advanced packaging can improve what a system can do, but it also creates more interfaces to check and more ways for one design decision to affect another. Better connected design and verification tools could help teams catch problems earlier, when changes are easier to make.

The collaboration also shows where AI may find a useful role in engineering. A design rule violation has a specific context and a result that can be checked with established software. That gives an AI agent a bounded task and a way to test its work. Even so, a passing check does not prove that a change is the best choice for the whole chip. Engineers will still need to judge trade-offs, especially when a fix affects timing, power or reliability.

There is an ecosystem effect, too. When design tools are certified for a manufacturer’s processes and packaging technologies, chip companies can use those flows with greater confidence. Siemens and TSMC are also extending training resources to TSMC design partners, which may help more teams learn the methods needed for advanced nodes.

Bottom line: For chipmakers, the value of this announcement will ultimately depend on measured results: fewer hours spent resolving violations, faster design cycles, and chips that meet their targets when manufactured. The companies have outlined an ambitious direction. The next test is whether these connected tools deliver those gains consistently on complex customer designs.

Contact Siemens

Contact TSMC

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TSMC OIP Ecosystem Forum 2026: Opening Remarks

TSMC OIP Ecosystem Forum 2026: Opening Remarks
by Mike Gianfagna on 09-28-2026 at 12:00 pm
Categories: 3D IC, AI, Events, Semiconductor, TSMC

TSMC OIP Ecosystem Forum 2026 Opening Remarks

The 2026 TSMC Open Innovation Platform (OIP) Ecosystem Forum was held on September 23, 2026, in Santa Clara, CA. This is the event where TSMC showcases the substantial progress made with its massive semiconductor ecosystem. As one would expect, AI was a key topic throughout the day, with some very impressive results reported and some exciting exhibits from both established and new companies.

You can get an excellent overview of the entire event on SemiWiki here. In this post, I will cover the opening remarks delivered by two of TSMC’s executives. These presentations set the stage for what followed. It was a packed day of memorable presentations and eye-catching exhibits. So, let’s examine the TSMC OIP Ecosystem Forum 2026 opening remarks

Sajiv Dalal Kicks Off the Day

Sajiv Dalal

Sajiv Dalal is the President and Chief Executive Officer of TSMC North America. In the graphic at the top of this post, you can see him on the massive stage, surrounded by so many partner logos.

Artificial intelligence is no longer a future trend. It is already transforming industries, driving massive infrastructure investment, and creating an entirely new wave of semiconductor innovation.

That was the message from Sajiv at the opening of TSMC’s 2026 OIP Ecosystem Forum, where he pointed to an industry that has now crossed the $1.7 trillion mark and to AI infrastructure spending that he said reached roughly $1 trillion this year. Over the next several years, that investment is expected to grow dramatically as AI becomes increasingly embedded in both business and everyday life.

He explained that the impact extends far beyond data centers. AI is moving rapidly toward the edge, accelerating advances in drug discovery, diagnostics, autonomous vehicles, manufacturing, warehousing, and countless other applications. Behind that progress is an increasingly sophisticated semiconductor technology stack spanning advanced process nodes, chiplets, packaging, interconnects, memory, power delivery, and system integration.

TSMC is positioning itself at the center of that transformation. Dalal highlighted innovations including nanosheet technologies, advanced stacking and packaging, next-generation HBM base die, backside power delivery, and integrated voltage regulation—all aimed at delivering the performance and power efficiency required by increasingly demanding AI systems.

But perhaps the most important theme of his speech was collaboration.

Dalal stressed that semiconductor innovation at this scale cannot happen in isolation. TSMC’s Open Innovation Platform brings together a broad ecosystem of partners that collaborate early, co-optimize technologies, and work toward first-time silicon success.

The forum itself reflects that philosophy, bringing together TSMC technologists, customers, and partners for market outlooks, technical deep dives, and dozens of presentations across AI/HPC, mobile, automotive, and other applications.

The takeaway was clear: AI may be driving the semiconductor industry’s next major growth cycle, but collaboration across the ecosystem will determine how quickly—and successfully—that opportunity becomes reality.

Dr. Lipen Yuan Expands on the Vision

Dr. Lipen Yuan

Dr. Lipen Yuan is Vice President, Business Development at TSMC.  He began by pointing out that:

AI is not simply creating a new class of semiconductor products—it is forcing the industry to rethink how chips are designed, integrated, and brought to market. Dr. Yuan framed this shift as both an extraordinary growth opportunity and a fundamental engineering challenge: the next phase of AI will require innovation across the entire technology stack, backed by a much more tightly integrated ecosystem.

The scale of the opportunity is already visible. Dr. Yuan described what he called a “golden era” for semiconductors, noting that an industry once expected to reach the $1 trillion milestone around 2030 has moved dramatically faster as AI demand has surged, with the market now approaching $1.7 trillion.

At the center of TSMC’s strategy is its Open Innovation Platform (OIP), which has spent nearly two decades bringing together foundry technology, EDA tools, intellectual property, cloud infrastructure, design services, packaging, and manufacturing expertise. Dr. Yuan pointed out that this collaborative model has helped lower barriers to chip development and enabled innovators worldwide to turn advanced semiconductor technologies into differentiated products.

That ecosystem is becoming even more important as AI moves beyond the cloud into edge devices, automotive systems, physical AI, and other emerging applications. These workloads are driving enormous increases in compute demand while simultaneously placing pressure on memory bandwidth, interconnect performance, power consumption, cooling, and system efficiency.

According to Yuan, the industry can no longer optimize individual chips in isolation. Future AI platforms will require system-wide co-design spanning advanced logic, packaging, memory, interconnects, power delivery, cooling, and networking. TSMC therefore sees the industry expanding from traditional design-technology co-optimization, or DTCO, toward broader system-technology co-optimization, or STCO.

Advanced packaging is another critical part of this shift. Yuan highlighted TSMC’s 3DFabric Alliance, which brings together memory, EDA, test, OSAT, and other partners to address the thermal, mechanical, and integration challenges associated with increasingly complex multi-die systems.

But perhaps the most forward-looking portion of the speech focused on using AI itself to design the chips that power AI.

Yuan said TSMC is already seeing meaningful productivity gains from AI-assisted semiconductor design. The company is now taking the next step with the introduction of the TSMC AI Design Kit, or ADK. Designed to complement traditional process design kits and established EDA flows, the ADK is intended to support emerging agentic AI design methodologies. TSMC envisions a future in which engineering teams create orchestration layers of AI agents and specialized skills that work alongside—or potentially replace portions of—traditional CAD flows.

The broader message was clear: scaling AI is no longer simply a matter of building faster silicon. It is becoming a system-level engineering challenge that requires deeper collaboration across the entire semiconductor ecosystem.

For TSMC and its partners, the opportunity is not simply to build chips for the AI revolution, but to use AI, advanced packaging, and system-level optimization to reinvent how those chips are designed in the first place.

To Learn More

There will be more posts on TSMC OIP Ecosystem Forum 2026. The event delivered rich content across many aspects of advanced chip development and highlighted the achievements of TSMC’s ecosystem partners. You can access an overview of TSMC OIP here. And that’s a summary of the TSMC OIP Ecosystem Forum 2026 opening remarks.

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Designing chips for the AI era: what TSMC’s roadmap means

Designing chips for the AI era: what TSMC’s roadmap means
by Daniel Nenni on 09-25-2026 at 8:00 am
Categories: 3D IC, AI, Events, Semiconductor, TSMC

TSMC LC Lu OIP Event

Dr. LC Lu TSMC OIP Forum 2026

About twenty years ago I worked with Cliff Hou, LC Lu, and the TSMC PDK team on reference flows with emerging EDA and IP companies. This was the precursor to the OIP. Having a person with LC Lu’s depth of R&D experience running the TSMC Design & Technology Platform is truly an honor, absolutely.

AI is creating two related problems for semiconductor designers. They must deliver more computing power for training and inference, while keeping energy use and cost manageable. Dr. LC Lu’s presentation at the TSMC Open Innovation Platform Forum describes a response built around more efficient transistors, closer integration of logic and memory, larger multi-chip packages, optical connections, and AI-assisted chip design.

The central challenge is useful work per unit of energy. An AI system’s cost is shaped not only by how quickly its processors calculate, but also by how much power they draw and how efficiently they receive data. Training a model requires immense computation. Serving that model to users adds a different burden: every generated token consumes processing, memory access and communication capacity. As inference use grows, small improvements in energy per token can have large effects across a data center.

The first part of TSMC’s approach is continued process improvement. New semiconductor processes can improve power, performance and area, the three measures commonly shortened to PPA. The presentation discusses nanosheet transistors and design technology co-optimization, in which engineers adapt circuit design and manufacturing technology together. A transistor alone does not determine a chip’s efficiency. Standard-cell layouts, wiring, placement and the demands of a particular workload all affect the result. TSMC has described its NanoFlex family as giving designers choices that help balance performance and energy efficiency.

Those choices matter because AI hardware is not uniform. A component designed for maximum speed may justify a different circuit layout from one designed for lower power or smaller area. Even within a single system, designers may use different kinds of cells where speed is critical and where it is less important. This is a practical limit on any simple claim that a newer manufacturing process will automatically make every AI workload cheaper: designers still have to turn the process’s capabilities into a working product.

The second part of the roadmap moves beyond the individual chip. AI processors need to exchange enormous amounts of data with high-bandwidth memory, or HBM. If computation becomes faster while memory access does not, processors can spend time waiting for data. Placing memory close to compute through advanced packaging increases the bandwidth available between them and can reduce the energy needed to move each bit. The presentation discusses a hierarchy of memory technologies rather than one universal replacement, reflecting different trade-offs in capacity, bandwidth, latency and power.

Advanced packaging also lets designers combine multiple computing dies in one system. TSMC’s CoWoS technology is an example of this approach, while its 3DFabric portfolio includes three-dimensional stacking. The attraction is scale: engineers can bring together more logic and memory than would fit comfortably on one conventional die. The difficulty is that package size, electrical connections, heat removal, power delivery, testing and manufacturing yield all become system-level design problems. TSMC’s 2026 forum materials place 3DFabric and advanced packaging alongside its leading-edge processes as essential parts of future AI design.

As systems grow, communication between them becomes another constraint. The presentation points to TSMC-COUPE, its compact optical engine, as a path toward high-bandwidth, energy-efficient networking. Optical links use light to carry information and may help where electrical links become costly in power or difficult to scale over distance. This does not mean every wire inside a chip disappears. It means designers are looking for the right connection at each level—from circuitry within a die to communication between large AI systems. TSMC lists co-packaged optics among the technologies featured at its 2026 forum.

The presentation’s other major theme is design productivity. More elaborate processes and packages create more decisions for engineers and more conditions their designs must satisfy. Electronic design automation, or EDA, tools already help turn a circuit plan into a physical layout and check whether it can be manufactured. The presentation describes a proposed AI-oriented design enablement kit and agent-based workflows that could help optimize placement and routing, identify and fix design-rule violations, migrate existing designs, and translate descriptions of three-dimensional chip architectures into a standard design format.

These are consequential tasks, but automation must be judged by the quality of the finished design, not only by how quickly a tool produces an answer. A proposed change still has to meet electrical, thermal, timing and manufacturing requirements. An AI agent may generate options and run repeated tool flows around the clock; engineers and verified design tools must establish that the result works. TSMC describes autonomous AI workflows with its ecosystem partners as a focus of the 2026 forum, while its established Open Innovation Platform brings together design tools, intellectual property and manufacturing guidance.

Shared design descriptions matter in this setting. LC Lu discusses 3Dblox as a way to describe complex multi-die architectures so that different tools and organizations can work from consistent information. TSMC previously introduced 3Dblox for three-dimensional chip design, with the goal of improving interoperability among design tools. For a package assembled from several dies, that common representation can reduce the risk that teams make incompatible assumptions about connections or physical arrangement.

Bottom line: AI progress increasingly depends on improving a whole computing system, not merely making one processor faster. Memory bandwidth, package integration, networking, energy supply and the time needed to design and validate a product can each become the limiting factor. TSMC’s presentation describes these constraints as connected engineering problems: improve the silicon, bring components closer together, move data more efficiently and help designers manage the resulting complexity.

TSMC OIP Forum 2026

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