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Intel and TSMC Take Different Paths to High-NA EUV

Intel and TSMC Take Different Paths to High-NA EUV
by Daniel Nenni on 08-07-2026 at 8:00 am
Categories: Lithography, Semiconductor, TSMC
6 Comments

Intel TSMC HNA EUV 2026

Intel and TSMC are pursuing the same objective—manufacturing smaller, faster, and more energy-efficient semiconductors—but they have adopted different strategies for advanced lithography. Intel moved early to develop High-Numerical-Aperture Extreme Ultraviolet lithography, commonly called High-NA EUV, while TSMC has continued extending conventional EUV for its latest production processes. Their choices reflect different technology roadmaps, manufacturing priorities, and assessments of cost and risk.

Conventional EUV lithography uses 13.5-nanometer light and projection optics with a numerical aperture of 0.33. It has become essential to producing advanced logic chips because it can print much smaller structures than earlier deep-ultraviolet systems. High-NA EUV uses the same wavelength but increases the numerical aperture to 0.55. This enables approximately 1.7 times better resolution and may allow manufacturers to print some critical patterns with one exposure instead of using multiple patterning steps.

Intel became the first chipmaker to receive ASML’s commercial High-NA development system, the TWINSCAN EXE:5000. Installed at Intel’s research facility in Hillsboro, Oregon, the system has been used to develop processes, materials, masks, and design rules for future manufacturing technologies. Intel plans to introduce High-NA EUV into its Intel 14A process, following Intel 18A, while continuing to use conventional EUV and other lithography methods where they offer better economics.

The early commitment supports Intel’s effort to restore semiconductor process leadership and expand its contract-manufacturing business. High-NA EUV gives Intel an opportunity to build expertise before the technology becomes widely used, while potentially simplifying the production of its most critical chip layers. Replacing a multi-patterning sequence with a single exposure could reduce the number of masks and processing steps, shorten manufacturing cycles, and limit errors caused by aligning multiple patterns. Early adoption could therefore provide both a technical advantage and an important point of differentiation for Intel Foundry.

TSMC has followed a more cautious path. The company concluded that it could manufacture its A16 and A14 generations without immediately introducing High-NA EUV into volume production. Instead, TSMC has continued improving its established 0.33-NA EUV platform through better masks, photoresists, overlay control, computational lithography, process optimization, and design-technology co-optimization. Innovations such as nanosheet transistors, backside power delivery, and more flexible standard-cell architectures also provide performance and density improvements that do not depend entirely on lithographic resolution.

Economics are central to TSMC’s decision. High-NA systems are considerably more expensive than conventional EUV scanners and require a new supporting ecosystem. Their anamorphic optics also produce an exposure field only half the size of a conventional EUV field. That limitation can complicate the manufacture of large processors and AI accelerators, potentially requiring two patterns to be stitched together. High-NA also presents challenges involving depth of focus, photoresist performance, masks, inspection, metrology, and yield.

TSMC operates conventional EUV at enormous scale and has accumulated extensive experience maximizing its productivity and reliability. Continuing to use that mature infrastructure reduces execution risk and allows the company to obtain greater returns from its existing equipment.

For an ultra high-volume foundry serving many customers, a proven process with stable yields may be more valuable than introducing the highest-resolution tool before its financial benefits are clear.

This does not mean TSMC has rejected High-NA EUV. The company has purchased equipment for research and has begun developing High-NA lithography technology for future processes. TSMC is ASML’s largest customer, and TSMC CEO C.C. Wei has repeatedly said that the two companies are working closely on High-NA EUV.

TSMC has said that adoption will depend on measurable manufacturing benefits, technology maturity, and cost. Intel is similarly not replacing every conventional EUV exposure with High-NA; it will use the new technology selectively on layers on internal products where its resolution creates sufficient value.

Bottom line: The difference is therefore primarily one of timing. Intel is accepting the cost and risk of being an early adopter in exchange for earlier learning and possible process leadership. TSMC is extending a mature technology while waiting for High-NA EUV to demonstrate stronger production economics. Both strategies may ultimately lead to High-NA manufacturing, but they represent distinct routes toward the next generation of semiconductor scaling.

We’ve discussed this extensively in the SemiWiki Forum, where several lithography experts have weighed in. As always, politically incorrect comments are welcome!

Also Read:

ASML High-NA EUV is Not Ready for High-Volume Production

Crossing the Yield Cliff: IDP V6 and the Future of Manufacturing Forecasting

Beyond Moore’s Law: High NA EUV Lithography Redefines Advanced Chip Manufacturing

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Executive Interview with James Huang of AlChip

Executive Interview with James Huang of AlChip
by Daniel Nenni on 08-03-2026 at 2:00 pm
Categories: 3D IC, Alchip, Chiplet, Semiconductor, Semiconductor Services, TSMC

James Huang

I had a chance sit down with James Huang, Director of Engineering at Alchip Technologies, to discuss the company’s recent multi-die packaging achievements and learn about Alchip’s next steps in pushing the boundaries of innovation for next generation AI ASIC.

James is acknowledged as a leading light in advanced node ASICs, based on his 25 years of SoC design and implementation experience. Prior to Alchip, he held key engineering and technical management positions at Simplex Solutions and Cadence Design Systems, Inc.

AI and HPC designs are pushing advanced packaging into the mainstream. From Alchip’s perspective, what is driving customer demand for TSMC CoWoS-based ASIC solutions now?

AI has fundamentally changed the design priorities for advanced silicon. A few years ago, advanced packaging was viewed as an optimization for a limited number of high-end applications. Today, it has become an architectural requirement for many AI and HPC designs.

The primary reason is that compute performance is no longer scaling fast enough on its own. Our customers tell us they need to combine multiple compute chiplets with HBM and high-speed I/O, while staying within practical limits for power, yield, and manufacturability. CoWoS provides a mature platform for achieving that level of integration.

Another important trend is that more companies, including hyperscalers and AI startups, are developing custom silicon. They are looking for differentiated architectures rather than off-the-shelf solutions. Advanced packaging is one of the key enablers of that differentiation.

For Alchip, this aligns closely with one of our core strengths: delivering complex custom ASICs through close collaboration with customers and ecosystem partners.

Where does Alchip see CoWoS fitting within the broader custom ASIC design flow, especially for AI accelerators, networking processors, and other high-performance designs?

We don’t see CoWoS as a packaging technology that is added at the end of a project. We see it as an integral part of the system architecture. For AI accelerators, networking processors, and HPC devices, packaging decisions influence many other aspects of the design, including die partitioning, floor planning, memory architecture, power delivery, thermal management, and verification.

That is why successful CoWoS programs require silicon and package co-design from the earliest planning stages. Our engineering teams work closely with foundry, packaging, IP, and EDA partners to ensure these decisions are made holistically, rather than sequentially.

Alchip has experience with both CoWoS-S and CoWoS-R. Can you summarize the company’s track record with these technologies and the types of customer programs they have supported?

Over the past several years, Alchip has participated in multiple advanced-node ASIC programs using both CoWoS-S and CoWoS-R technologies across AI, HPC, and networking applications.

While we can’t discuss customer-specific projects, these engagements have helped us build deep experience in silicon-package co-design, HBM integration, power integrity, thermal optimization, and manufacturing collaboration.

Each successful project strengthens our internal methodologies and increases our confidence in supporting increasingly complex heterogeneous integration platforms.

For readers who follow advanced packaging closely, how would you compare the design considerations for CoWoS-S versus CoWoS-R? Where does each technology tend to fit best?

These technologies address different optimization points:

CoWoS-S is based on a silicon interposer. It offers the highest interconnect density and is optimized for bandwidth-intensive applications, such as AI training accelerators with multiple HBM stacks.

CoWoS-R uses redistribution layers. It provides greater flexibility and cost advantages for designs that do not require ultra-high routing density.

Rather than viewing them as competing technologies, we see them as complementary options. The optimal choice depends on the device architecture, bandwidth requirements, package size, and cost objectives.

What are the most important front-end design decisions that influence success in a CoWoS-based ASIC program?

One of the most important lessons we have learned is that architectural decisions made early in the project have a disproportionate impact on overall program success.

These decisions include chiplet partitioning strategy, HBM organization, die size optimization, power budgeting, and package selection.

Each of these choices influences yield, manufacturability, verification complexity, and ultimately time-to-market.

Investing sufficient effort during the architecture phase can significantly reduce downstream design iterations.

What are the key architectural tradeoffs designers should evaluate when considering chiplet partitioning and memory integration?

There is no single optimal partitioning strategy.

Customers need to balance multiple considerations, including bandwidth versus latency, die size versus yield, process-node optimization, power efficiency, and package complexity.

Similarly, memory integration should be evaluated as part of the overall system architecture, rather than as an isolated component.

Our role is to evaluate these tradeoffs objectively and identify the solution that best fits the customer’s product goals.

What are the major power-delivery challenges in large CoWoS designs today?

Power density continues to increase rapidly, particularly in AI accelerators.
Today’s large multi-chip packages require careful coordination across silicon, package, and board design to maintain stable power delivery, minimize IR drop, and preserve signal integrity.

One trend we see clearly is that power delivery is becoming a system-level challenge, rather than only a chip-level challenge.

This reinforces the importance of cross-domain collaboration throughout the design process.

Thermal performance is another major design constraint. How early does thermal analysis begin, and what tradeoffs does it create in die placement, floor planning, package selection, and system-level design?

Thermal considerations should be addressed much earlier in the design process than many people think.

For advanced AI ASICs, thermal analysis starts during architectural planning because chiplet placement, high-bandwidth memory arrangement, power distribution, and package selection all strongly influence the cooling strategy. At this stage, engineers can evaluate how each architectural choice affects heat generation, heat movement through the package, and heat removal at the system level.

Waiting until physical implementation to address thermal issues often leads to costly redesigns.

Early thermal co-analysis enables more balanced tradeoffs among performance, manufacturability, reliability, and system-level cooling requirements.

What key verification challenges are unique to CoWoS designs?

Verification complexity increases significantly in heterogeneous multi-die systems compared with traditional single-die implementations.
In CoWoS-based designs, verification extends beyond silicon functionality. It must also account for interactions across die-to-die interfaces, package behavior, power delivery, thermal conditions, and system-level operating requirements.

The industry is moving toward more integrated verification methodologies that evaluate silicon and package behavior together, rather than independently.

Beyond design, successful CoWoS programs depend on manufacturing and supply-chain execution. What issues are most critical, particularly around capacity, yield, test strategy, and production ramp?

CoWoS programs require close coordination across multiple ecosystem partners, including foundry, packaging, memory, test, and assembly resources.
Key considerations include packaging capacity, HBM availability,manufacturing yield, test strategy, production scheduling, and ramp execution.

Successful execution depends not only on technical excellence, but also on disciplined program management across the entire supply chain.

This is an area where experienced ASIC service providers can create significant value for customers by helping align technical requirements, partner schedules, supply availability, and production milestones.

Without discussing customer-specific programs, what opportunities does Alchip see for CoWoS-L?

CoWoS-L represents another important step in heterogeneous integration.
As AI systems continue to scale, customers will need larger packages, higher interconnect density, and greater flexibility in integrating multiple functional chiplets.

We believe CoWoS-L will support new classes of AI and HPC systems that require higher levels of scalability than current packaging technologies can efficiently provide.

Alchip is actively preparing its design methodologies to support these future architectures.

Looking ahead, how does Alchip expect CoWoS-S, CoWoS-R, and CoWoS-L to evolve? As AI ASICs move to larger die, more chiplets, higher HBM capacity, and more demanding performance-per-watt targets, how should customers think about choosing among these options?

We expect CoWoS-S, CoWoS-R, and CoWoS-L to coexist because each addresses different design and market requirements.

Future AI ASICs will require more chiplets, higher HBM bandwidth and capacity, heterogeneous process technologies, more sophisticated power delivery, and stronger silicon-package co-optimization.

As these requirements increase, designers are unlikely to converge on a single packaging technology. Instead, they will select different CoWoS options based on their architecture, bandwidth requirements, package size, power objectives, manufacturability needs, schedule, and cost targets.

From Alchip’s perspective, the goal is not to promote one packaging technology over another. It is to help designers evaluate and implement the solution that delivers the best balance of performance, manufacturability, schedule, and total system cost.

Also Read:

Alchip Accelerates on AI ASIC Demand

AI Chip Design Moves Beyond Monolithic Silicon with Alchip 3DIC

Alchip’s Leadership in ASIC Innovation: Advancing Toward 2nm Semiconductor Technology

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The Difference Between TSMC CoWoS-S and CoWoS-R

The Difference Between TSMC CoWoS-S and CoWoS-R
by Daniel Nenni on 07-31-2026 at 6:00 am
Categories: 3D IC, AI, Semiconductor, TSMC
2 Comments

The Difference Between CoWoS S and CoWoS R

CoWoS-S and CoWoS-R are two versions of TSMC’s Chip-on-Wafer-on-Substrate advanced packaging platform. Both technologies are designed to combine high-performance processors, chiplets and high-bandwidth memory, or HBM, within a single package. This shortens the electrical connections between computing and memory components, enabling higher bandwidth and better energy efficiency than conventional packaging. Their main difference lies in the material and structure used for the interposer that connects the chips.

CoWoS-S uses a silicon interposer. The “S” therefore refers to silicon. Logic dies and HBM stacks are mounted on a large piece of silicon containing extremely dense metal wiring. Through-silicon vias, or TSVs, carry electrical signals and power vertically through the interposer to the package substrate beneath it. Because semiconductor manufacturing processes can create very fine wiring on silicon, CoWoS-S offers exceptionally high interconnection density. TSMC also integrates embedded deep-trench capacitors into the silicon interposer, helping stabilize power delivery for demanding processors.

These characteristics make CoWoS-S particularly suitable for systems requiring the highest possible communication density between processors and memory. Its mature silicon-based design has been in production since 2012 and has been widely used in high-performance computing and artificial-intelligence accelerators. TSMC states that current CoWoS-S technology can support silicon interposers as large as approximately 3.3 reticle sizes, or about 2,700 square millimetres.

However, manufacturing a very large silicon interposer is technically difficult and expensive. The interposer must be produced using wafer-fabrication equipment, and its dimensions are constrained by lithography, wafer processing, yield and mechanical considerations. As packages expand to accommodate more computing dies and HBM stacks, producing a single, defect-free silicon interposer becomes increasingly challenging.

CoWoS-R addresses this scaling problem by replacing the silicon interposer with a redistribution-layer interposer. The “R” refers to RDL. Instead of being formed from a solid silicon wafer, the interposer consists mainly of polymer dielectric layers and copper wiring. TSMC’s CoWoS-R entered volume production in 2023. Its RDL interposer presently supports routing with a minimum pitch of four micrometres, corresponding to copper lines and spaces of approximately two micrometres each.

The RDL structure is less rigid than silicon. Its mechanical flexibility helps absorb stresses caused by differences in thermal expansion between the chips, interposer and organic package substrate. This can improve the reliability of the C4 solder joints connecting the interposer to the substrate. TSMC research has shown that multiple RDL layers can act as a stress buffer and provide strong joint reliability in large heterogeneous packages.

CoWoS-R also offers greater package-size scalability. TSMC recommends CoWoS-R or CoWoS-L when the required interposer exceeds approximately 3.3 reticle sizes. The RDL platform can therefore be attractive for extremely large AI and HPC packages containing numerous chiplets or memory stacks. Its copper routing can provide good signal and power integrity, while avoiding the need to manufacture one enormous silicon interposer.

The trade-off is that CoWoS-R generally does not provide the same interconnect density or integrated capacitor capability as a full silicon interposer. CoWoS-S remains the stronger choice where maximum wiring density, mature performance and tightly integrated power-delivery features are the priorities. CoWoS-R is more appropriate where package size, mechanical flexibility, scalability and potentially simpler large-area manufacturing are more important.

Bottom Line: CoWoS-S prioritizes maximum interconnect density and electrical performance through a silicon interposer, whereas CoWoS-R prioritizes large-package scalability and mechanical flexibility through a polymer-and-copper RDL interposer. Both support advanced heterogeneous integration, but they solve different engineering challenges within modern AI and high-performance computing systems.

Also Read:

TSMC CoPoS Versus Intel EMIB Semiconductor Packaging

TSMC CoWoS versus Intel EMIB Semiconductor Packaging

TSMC A16 Backside Power at VLSI 2026

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TSMC CoPoS Versus Intel EMIB Semiconductor Packaging

TSMC CoPoS Versus Intel EMIB Semiconductor Packaging
by Daniel Nenni on 07-24-2026 at 10:00 am
Categories: Chiplet, Intel Foundry, Semiconductor, TSMC
2 Comments

TSMC CoPos Versus Intel EMIB 2026

TSMC’s CoPoS, generally described as Chip-on-Panel-on-Substrate, and Intel’s EMIB, or Embedded Multi-die Interconnect Bridge, address the same strategic problem: integrating increasingly large, heterogeneous chiplet systems. However, they attack different physical constraints. CoPoS is an emerging panel-level packaging platform intended to extend interposer scale and manufacturing productivity beyond round wafers. EMIB is a production-proven localized silicon-bridge architecture that removes the need for a full-size silicon interposer. TSMC has confirmed that CoPoS is under development, although detailed public specifications remain limited.

In CoPoS, redistribution structures and chip-integration processes are performed on a large rectangular panel rather than a circular silicon wafer. The rectangular format can improve area utilization because packages tile more efficiently, reducing unused edge area. More importantly, panel dimensions can support package footprints beyond practical wafer and reticle-derived limits. This makes CoPoS attractive for future AI accelerators combining multiple compute dies, I/O dies, and numerous high-bandwidth-memory stacks. Nevertheless, interconnect pitches, qualified materials, yields, reliability data, and production schedules are less publicly defined than those of TSMC’s established CoWoS platform.

EMIB uses small silicon bridge dies embedded locally inside an organic package substrate. Fine-pitch microbumps connect adjacent chiplets to high-density wiring within each bridge, while conventional substrate routing handles lower-density signals and power elsewhere. Because silicon is placed only where dense die-to-die communication is required, EMIB avoids the area, cost, and through-interposer routing burden of a monolithic silicon interposer. Intel positions EMIB for logic-to-logic and logic-to-HBM connections and reports that the technology has supported mass production since 2017.

The primary architectural distinction is global versus local integration. CoPoS is best understood as a manufacturing and scaling framework for constructing very large interposer or redistribution-layer assemblies across a panel. It can provide broad routing connectivity among many dies and memory stacks, resembling a larger-format evolution of wafer-level 2.5D integration. EMIB instead creates point-to-point shoreline links between neighboring dies. This modularity lets designers deploy multiple bridges with link-specific routing while preserving much of the organic substrate for conventional power and external I/O distribution.

These choices produce different electrical trade-offs. A broad CoPoS redistribution fabric could simplify complex multi-die topologies and support extensive fan-out, but long global routes may introduce resistance, capacitance, latency, and signal-integrity challenges. Panel warpage, lithographic uniformity, overlay accuracy, and fine-line yield across a large rectangular area are also central process risks. EMIB minimizes high-density silicon routing length and does not force unrelated power or signals through a full interposer. However, its localized geometry requires careful chiplet placement, bridge alignment, escape routing, and die-edge bandwidth planning. Communication between nonadjacent dies may require additional bridges or package-level hops.

Thermally, neither technology eliminates the difficulty of cooling tightly packed AI silicon and HBM. CoPoS may enable extremely large assemblies, increasing total package power, mechanical stress, and cooling complexity. EMIB’s absence of a full silicon interposer can reduce some structural and routing constraints, but high-power chiplets still require advanced heat spreaders, substrate engineering, and power delivery. Intel’s EMIB-M incorporates metal-insulator-metal capacitors, while EMIB-T adds through-silicon vias to strengthen power delivery and support HBM-oriented configurations.

Ecosystem compatibility also differs today: CoPoS will likely benefit customers already using TSMC’s 3DFabric design flows, foundry nodes, and HBM assembly ecosystem, whereas EMIB integrates dies from Intel or external foundries and can be combined with Foveros stacking to create more complex 3.5D systems.

Manufacturing maturity is currently EMIB’s clearest advantage. Its product history provides validated assembly flows, reliability experience, and established design methodology. CoPoS offers potentially greater package-scale economics and geometric freedom, but panel-level semiconductor packaging must achieve wafer-like overlay, cleanliness, defect control, and yield before competing broadly.

Bottom line: CoPoS and EMIB are not direct substitutes. CoPoS targets the scaling of the integration canvas; EMIB optimizes where high-density connections are physically necessary. For near-term heterogeneous products requiring proven, flexible local interconnects, EMIB is lower risk. For future ultra-large AI systems constrained by wafer-format area and throughput, CoPoS could provide a more expansive platform—provided TSMC converts panel-level scale into acceptable interconnect density, warpage control, reliability, and cost.

Also Read:

TSMC CoWoS versus Intel EMIB Semiconductor Packaging

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The Silicon Shield Has Never Been Stronger!

The Silicon Shield Has Never Been Stronger!
by Daniel Nenni on 07-24-2026 at 6:00 am
Categories: China, Semiconductor, TSMC
3 Comments

The Taiwan Silicon Shield

The “Silicon Shield” describes the idea that Taiwan’s central role in advanced semiconductor manufacturing raises the economic and strategic cost of military action against the island. The shield is not a literal defense system. It is a form of structural deterrence created by technological concentration: governments and firms depend on Taiwanese fabrication capacity, especially the leading-edge logic chips produced by Taiwan Semiconductor Manufacturing Company (TSMC). Because these chips enable artificial intelligence accelerators, smartphones, cloud servers, telecommunications equipment, vehicles, and advanced weapons, a conflict that disabled Taiwan’s semiconductor sector would transmit severe shocks through the global economy.

The shield originates in the semiconductor industry’s vertically disaggregated architecture. Many American and European firms specialize in chip design, electronic-design automation software, semiconductor intellectual property, manufacturing equipment, or materials, while relying on dedicated foundries for physical production. TSMC’s pure-play foundry model allows competing fabless companies to manufacture designs without building their own fabrication plants. This model also creates economies of scale: process research, equipment utilization, yield learning, and customer demand are concentrated in one manufacturing platform. In 2025, TSMC reported more than 17 million twelve-inch-equivalent wafers of annual available capacity and produced thousands of products across hundreds of process technologies. Much of its core fabrication network remains in Taiwan, despite new facilities abroad. My first book “Fabless: The Transformation of the Semiconductor Industry” is based on this. I had a ringside seat to this transformation during my 40+ semiconductor career and it was quite the experience, absolutely.

Today, TSMC dominates the leading edge process technologies required for AI at 3nm and 2nm with scant alternatives due to time-to-market, cost, capacity, and the supporting ecosystem. 1.4nm is the next battle ground,  unfortunately Samsung is struggling with struggling with 2nm and Rapidus does not have enough capacity to make a difference. Intel 14A, however,  is definitely a contender for the NOT TSMC market. The Intel 14A and TSMC A14 PDKs will be ready for tape-out in Q1 2027 with HVM in 2028. The race is on!

Technically, advanced semiconductor capacity cannot be reproduced quickly. A leading-edge fab costs tens of billions of dollars, requires highly specialized extreme-ultraviolet lithography, ultrapure chemicals, stable electricity and water, precision metrology, and a dense network of engineers and suppliers. Physical equipment alone is insufficient. High-volume manufacturing depends on tacit process knowledge, statistical process control, defect reduction, and years of yield optimization. A nominally identical production line in another country may therefore take substantial time to achieve comparable throughput, reliability, and cost.

This concentration creates deterrent value because all major powers would suffer from disruption. The United States depends on Taiwanese manufacturing for chips designed by firms such as Apple, Nvidia, AMD, and Qualcomm. China also depends on imported advanced processors and on electronics supply chains connected to Taiwan. Japan, South Korea, and Europe would face shortages affecting industrial machinery, automobiles, communications, and defense production. In addition, the Taiwan Strait is itself a major commercial corridor; CSIS estimated that about $2.45 trillion in goods transited it in 2022. A blockade or invasion would therefore damage semiconductor production and wider maritime trade simultaneously.

However, the silicon shield has important limitations. Economic interdependence does not automatically prevent war when political leaders prioritize sovereignty, nationalism, or regime legitimacy over commercial losses. Semiconductor facilities are also fragile. Electricity interruption, cyberattack, damaged ports, loss of specialist personnel, or interrupted imports of gases, chemicals, wafers, and spare parts could halt production without factories being physically destroyed. The shield may even create a strategic vulnerability by making Taiwan a uniquely valuable node whose control or denial could appear militarily significant.

Its operation also depends on expectations. Deterrence is strongest when potential aggressors believe disruption would be prolonged, foreign intervention plausible, and captured fabs unusable. Since advanced plants rely on international equipment, software updates, and customer cooperation, occupying the facilities would not automatically transfer a functioning semiconductor ecosystem.

Diversification further changes the shield’s strength. TSMC is expanding manufacturing in the United States and Japan, while governments are subsidizing domestic semiconductor ecosystems. Such investments improve supply-chain resilience but will not rapidly duplicate Taiwan’s complete cluster of advanced fabrication, packaging, suppliers, and engineering talent. Overseas fabs may reduce the world’s exposure to a single geographic point while leaving Taiwan essential for the most advanced processes and high-volume scaling.

Bottom line: Close your eyes and imagine a world without leading edge semiconductors. Most of us have lived long enough to know what that would be like. Now imagine that the only country with leading edge semiconductors is China and the rest of the world is back to the dark ages. Yes, that is how strong the Silicon Shield is, absolutely.

(Politically incorrect observations and opinions are welcome in the comments section since only registered members can see them.)

Also Read:

TSMC CoWoS versus Intel EMIB Semiconductor Packaging

TSMC’s Raises the Bar on CAPEX!

TSMC A16 Backside Power at VLSI 2026

Driving the Future through the “Talent Empowering Program”: Why TSMC Charity Foundation’s Youth Career Initiative Matters

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TSMC CoWoS versus Intel EMIB Semiconductor Packaging

TSMC CoWoS versus Intel EMIB Semiconductor Packaging
by Daniel Nenni on 07-17-2026 at 8:00 am
Categories: 3D IC, Intel Foundry, Semiconductor, TSMC
1 Comment

TSMC CoWoS verus Intel EMIB

There has been talk at the latest conferences about TSMC customers taking wafers to Intel for packaging. The question is why? Is it competitive pricing? Capacity? Supply chain diversity? CC Wei was asked about this during the last investor call and his perfect response was:

Jeff Su: I guess very simply put, EMIB-T, in his view, is gaining traction, how do we see the competitive threat from this?

C.C. Wei: Well, let me say that our packaging capacity is so tight that now it’s limiting my customers’ growth. We welcome that additional flexibility in the market. That will help TSMC’s front-end wafer business growth, which is a majority part of TSMC’s business. The technology looks good, according to the newspaper. We hope they will be successful, that share some of the loading from TSMC. Today, we’re working very hard to shorten the gap between the demand and the capacity. As I said, we welcome have this additional alternative, the flexibility for my customer.

What is the difference between TSMC CoWoS and Intel EMIB?

TSMC CoWoS and Intel EMIB are advanced packaging platforms designed to overcome the economic and physical limits of monolithic system-on-chip scaling. Both enable heterogeneous integration of logic, memory and specialized chiplets within one package, but they use fundamentally different interconnect structures. CoWoS generally creates a broad, high-density interconnect plane beneath the dies, whereas EMIB places small silicon bridges only where adjacent dies require dense communication. This architectural distinction drives differences in bandwidth distribution, package scaling, cost, thermal behavior and design methodology.

CoWoS, meaning Chip-on-Wafer-on-Substrate, is part of TSMC’s 3DFabric portfolio and is widely associated with high-performance computing and artificial-intelligence processors. In CoWoS-S, logic dies and high-bandwidth memory stacks are mounted on a passive silicon interposer containing fine-pitch wiring and through-silicon vias. The interposer is subsequently attached to an organic package substrate. Because almost the entire area under the active dies can provide dense routing, CoWoS-S supports extremely wide parallel interfaces, predictable signal paths and substantial die-to-die connectivity. TSMC states that CoWoS-S supports interposers up to approximately 3.3 reticles, or 2,700 square millimetres, while CoWoS-L and CoWoS-R support larger systems.

The CoWoS family is broader than a single silicon-interposer process. CoWoS-R replaces the large silicon interposer with a multilayer redistribution-layer interposer, reducing dependence on a complete sheet of interposer silicon. CoWoS-L combines an RDL-based interposer with localized silicon interconnect elements in regions requiring greater routing density. These variants allow designers to trade maximum wiring density against package size, cost and manufacturing complexity. Consequently, comparing EMIB only with CoWoS-S understates TSMC’s architectural flexibility. CoWoS-L, in particular, uses localized silicon structures that partially resemble bridge-based packaging. Both CoWoS-R and CoWoS-L entered volume production before or during 2024.

Intel’s Embedded Multi-die Interconnect Bridge embeds small passive silicon bridges inside an organic package substrate. Microbumps connect the edges of neighbouring dies to fine-pitch wiring on each bridge, while conventional substrate traces carry lower-density signals elsewhere. EMIB therefore avoids a package-wide silicon interposer and its associated through-silicon vias. Intel positions EMIB for logic-to-logic and logic-to-HBM integration and reports high-volume production use since 2017. Newer options include EMIB-M, which incorporates metal-insulator-metal capacitance, and EMIB-T, which adds through-silicon vias to the bridge for enhanced vertical connectivity and power delivery.

From an electrical perspective, CoWoS-S offers the most uniform high-density routing environment. A large interposer can distribute thousands of short connections among a central accelerator, multiple HBM stacks and additional chiplets without limiting dense links to die edges facing a bridge. This characteristic is especially valuable when broad connectivity is required across much of the package. The continuous interposer also permits designers to integrate power-distribution structures and decoupling capacitance close to active devices.

EMIB is more silicon-efficient when communication is localized between adjacent dies. It provides short, dense interconnections without paying the silicon-area cost of an interposer beneath components that do not require fine-pitch routing. However, complicated topologies may require multiple bridges, careful chiplet floorplanning and additional organic-substrate traces between nonadjacent components. The package architecture must align bridge locations precisely with the edges and interfaces of each die.

Mechanical and manufacturing trade-offs are similarly nuanced. Eliminating a large silicon interposer can reduce material usage and some wafer-processing operations, giving EMIB potential cost and yield advantages for appropriate designs. Its organic substrate remains difficult to manufacture because bridges must be embedded, planarized and aligned accurately. CoWoS-S adds a large, thin silicon structure whose fabrication, handling, warpage control and known-good-die assembly increase process complexity. Nevertheless, its regular interposer provides a mature and predictable routing platform. CoWoS-R and CoWoS-L attempt to reduce the size, cost and manufacturability constraints of full silicon interposers.

Neither architecture automatically solves heat removal. Both place high-power logic and HBM stacks in close proximity, increasing thermal coupling and local heat density. CoWoS can accommodate large logic-and-memory arrays, but package warpage, power delivery and cooling become harder as the interposer and package expand. EMIB permits relatively flexible die placement and avoids a continuous silicon layer, although thermal performance still depends principally on die power, spacing, heat-spreader design, package materials and system-level cooling.

Both technologies can also support vertical integration. Intel combines EMIB with Foveros die stacking to produce EMIB 3.5D systems containing multiple horizontally and vertically integrated chiplets. TSMC can combine CoWoS with its SoIC wafer-level stacking platform. These combinations allow designers to place cache, logic or specialized functions vertically while using CoWoS or EMIB for package-level horizontal connectivity.

The practical selection criterion is therefore connectivity geometry rather than a simple performance ranking. CoWoS-S is strongest when a system requires a large, continuous and extremely dense interconnect fabric, particularly between accelerators and multiple HBM stacks. CoWoS-R and CoWoS-L extend this approach toward larger or more cost-conscious products. EMIB is strongest when high-bandwidth links are concentrated at particular die boundaries and designers value silicon efficiency, modularity and avoidance of a full interposer.

Bottom line: CoWoS emphasizes an interposer-centric system fabric, while EMIB emphasizes localized silicon bridges embedded in an organic substrate. The better choice depends on interface width, communication topology, package dimensions, power delivery, thermal limits, assembly yield, design-tool support, manufacturing availability and total system cost—not on packaging density alone.

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TSMC’s Raises the Bar on CAPEX!

TSMC’s Raises the Bar on CAPEX!
by Daniel Nenni on 07-17-2026 at 6:00 am
Categories: AI, Semiconductor, TSMC

TSMC CAPEX 2026 SemiWiki

On the latest investor call the big story was the increase in CAPEX for 2026 and the expected CAPEX for 2027. TSMC raised the CAPEX ceiling for 2026 from US$56 billion to US$64 billion. My guess would be US$64 billion will be spent if not more. We have been discussing this in the SemiWiki Forum and my guess for the 2027 TSMC CAPEX is an incredible US$76 billion to US$80 billion.

This is a clear message to customers and competitors that leading edge capacity is guaranteed. 

“Our business in the second quarter was supported by strong demand for our leading-edge process technologies,” said Wendell Huang, Senior VP and Chief Financial Officer of TSMC. “Moving into third quarter 2026, we expect our business to be supported by continued strong demand for our leading-edge process technologies, including the steep ramp-up of our 2-nanometer technology.”

TSMC operates in one of the most capital-intensive industries in the world. Its ability to maintain technological leadership depends not only on research and development but also on sustained capital expenditure, commonly called CAPEX. These investments fund new fabrication plants, advanced lithography equipment, cleanrooms, utilities, packaging facilities, and upgrades to existing production lines. For TSMC, CAPEX is therefore both a financial commitment and a strategic tool for defending its leadership in semiconductor manufacturing.

TSMC’s recent spending plans reflect the rapid growth of artificial intelligence, high-performance computing, smartphones, and other data-intensive applications. At the beginning of the year, for 2026, the company indicated capital expenditure of approximately US$52 billion to US$56 billion, with spending expected toward the upper end of that range. That has since been revised to US$60 billion to US$64 billion and I feel spending will again be at the upper range. Most of the budget is directed toward advanced process technologies, particularly N3 and N2 capacity, while the remainder supports specialty technologies, advanced packaging, testing, mask production, and related infrastructure. This allocation shows that TSMC is investing across the entire manufacturing chain rather than concentrating only on wafer fabrication.

Capacity expansion is essential because semiconductor plants require long construction and qualification periods. A new fab can take 3-5 years to build, equip, test, and bring into volume production. TSMC must therefore make investment decisions well before customer demand is fully visible. Underinvestment could create shortages and cause major customers to seek alternative suppliers. Overinvestment, however, could leave expensive equipment underused and weaken returns. TSMC manages this risk by expanding capacity in phases, maintaining close relationships with customers, and prioritizing technologies where demand is expected to remain structurally strong.

Taiwan remains the center of TSMC’s most advanced manufacturing network. The company is expanding leading-edge production there, including 2-nanometer capacity, because Taiwan offers an established supplier ecosystem, experienced engineers, efficient infrastructure, and strong operational coordination. TSMC is also increasing advanced packaging capacity, especially technologies such as CoWoS, which are important for combining powerful processors with high-bandwidth memory in AI systems. Packaging has become a major bottleneck, so investment in backend capacity is now almost as strategically important as investment in advanced wafers.

At the same time, TSMC is building a more geographically diversified production footprint. In Arizona, it is developing a large manufacturing cluster intended to support advanced chip production in the United States. Its total  US investment has reached US$165 billion and has just announced another US$100B on the investor call for a total of US$265 billion covering multiple fabs and supporting facilities. TSMC is also expanding in Japan through its Kumamoto operations, which focus on technologies needed by automotive, industrial, consumer, and image-sensor customers. In Germany, its planned Dresden venture is designed mainly to serve European automotive and industrial demand.

This global expansion provides several benefits. It places production closer to major customers, improves supply-chain resilience, and responds to government concerns about semiconductor security. It may also help TSMC access subsidies, infrastructure support, and strategic partnerships. However, overseas fabs are generally more expensive to build and operate than facilities in Taiwan. Higher labor, construction, compliance, and supply-chain costs can reduce margins, while shortages of experienced workers may slow production ramp-ups. TSMC must balance geographic resilience with operational efficiency.

Bottom line: TSMC’s CAPEX and capacity expansion strategy is a long-term bet on continued semiconductor growth. The company is investing aggressively because advanced chips are becoming central to AI, cloud computing, communications, vehicles, and industrial automation. Its success will depend on matching capacity with real customer demand, executing overseas projects efficiently, and preserving technology leadership. If managed well, these investments will strengthen TSMC’s competitive position and reinforce its role as the world’s most important independent semiconductor foundry, absolutely.

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DAC 2026 See Analog Bits TSMC N2P IP portfolio and meet with its engineering experts!

DAC 2026 See Analog Bits TSMC N2P IP portfolio and meet with its engineering experts!
by Daniel Nenni on 07-15-2026 at 2:00 pm
Categories: Analog Bits, Events, GlobalFoundries, Intel Foundry, IP, Samsung Foundry, TSMC

Dac Banner

Analog Bits, Inc. is an established provider of mixed-signal semiconductor IP that integrates into advanced system-on-chip (SoC) designs to enable intelligent energy and power management. Its full portfolio of IP blocks includes precision clocking macros, power and temperature sensors including LDO and regulators, programmable interconnect solutions such as multi-rate SERDES and programmable I/O’s. These products help balance performance and power while optimizing system level power integrity in applications ranging from data centers, edge AI, computing and networking, to automotive, aerospace and consumer electronics.

Technically, Analog Bits addresses the most critical challenges of today’s power-hungry high-performance computing system needs, whatever the target application: to be power efficient, deliver good thermal management and maintain signal integrity at high data rates. The company’s low power mixed-signal IP portfolio sits at the intersection of all three: it determines how efficiently power is delivered on-chip, how accurately signals are timed, and how cleanly high-speed data moves through interconnects.

The company’s IP has been shipped at billions of units scale across customer designs and is proven in all major process technologies, including leading edge 2nm technology, with all five major global foundries: TSMC, Samsung Foundry, Intel Foundry, GlobalFoundries, RAPIDUS, UMC. Analog Bits has over 1,000+ IP products on 75+ process nodes and used by over 400 customers globally.

Specific customer names cannot be disclosed due to standard NDA practices, but Analog Bits’ IP can be found in top global hyperscalers’ AI accelerator programs; in leading North American automotive OEMs’ next-generation SoC programs; in major US big-tech custom silicon programs in the data-center; in hyperscale switch ASIC vendors and high-lane-count interconnect designers; and in the next generation of AI accelerators.

The core differentiator for Analog Bits’ IP is its process portability across nodes and foundries, its first-time silicon success track record, being pre-integrated and customizable for SoC platforms, and extremely low-power designs validated in silicon.

You can visit Analog Bits at DAC 2026 at booth number 949 to see live demonstrations of the company’s TSMC N2P IP portfolio and meet with its engineering experts. Also discover how Analog Bits’ advanced PLLs, power management solutions, and comprehensive infrastructure IP can help power the next generation of semiconductor innovation. For more information visit the web site at https://www.analogbits.com/.

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TSMC A16 Backside Power at VLSI 2026

TSMC A16 Backside Power at VLSI 2026
by Daniel Nenni on 07-10-2026 at 6:00 am
Categories: 3D IC, Semiconductor, TSMC

TSMC A16 Backside Power at VLSI 2026

TSMC’s A16 technology, presented as Paper T1.5 at the June 2026 IEEE/JSAP VLSI Symposium, marks the company’s first angstrom-class CMOS platform combining enhanced nanosheet gate-all-around transistors with backside power delivery. The key integration feature is Super Power Rail, or SPR, which TSMC describes as a backside direct-contact power delivery scheme targeted at AI and high-performance-computing designs with dense power grids and complex signal routing. Compared with N2P, the VLSI abstract reports 8–10% higher speed at the same power, or 15–20% lower power at the same speed, plus 8–10% chip-density gain, with mass production slated for Q4 2026.

The technical motivation is straightforward: at advanced nodes, frontside metal stacks are increasingly congested. Conventional power rails compete with signal interconnect for routing tracks, and resistive voltage loss, or IR drop, becomes harder to control as supply voltages fall and current density rises. By moving the primary power distribution network to the wafer backside, A16 separates power delivery from frontside signal routing. This releases frontside resources for timing-critical interconnect while creating a lower-resistance path for VDD/VSS delivery. TSMC’s public A16 page states that SPR improves logic density and performance by dedicating frontside routing to signals and significantly reducing IR drop.

A notable part of TSMC’s approach is the backside direct contact architecture. Rather than only placing large backside power metals underneath the device layer, SPR connects backside power more directly into the transistor source/drain region through backside vias and contacts. The VLSI technical tipsheet describes A16-SPR as using backside direct-contact power delivery, front/back-side metals, and 3D MIM capacitors, indicating that the power-delivery system is not merely a routing rearrangement but a full process-integration module.

This matters because backside power can create tradeoffs in cell height, device width, standard-cell architecture, and design-technology co-optimization. TSMC emphasizes that its backside contact scheme preserves N2P gate density and NanoFlex design flexibility, meaning designers can still tune cell layouts for performance, power, and area rather than being locked into a single restrictive cell template. The VLSI session abstract specifically says SPR preserves N2P gate density and NanoFlex DTCO benefits, which is important for real product implementation rather than only test-chip demonstration.

For AI and HPC chips, A16’s benefit is especially relevant. Large accelerators have massive simultaneous switching currents, long global routes, high SRAM/cache content, and strict timing closure requirements. Reducing IR drop improves effective transistor drive because less voltage is lost before reaching active devices. Freeing frontside routing also helps high-utilization logic blocks where congestion can otherwise force longer wires, more buffers, or larger cells. In practice, SPR should improve both electrical efficiency and physical-design closure, particularly for compute tiles, CPU cores, and accelerator fabrics.

Bottom line: A16 represents more than a node shrink. It is a structural change in how power and signals are partitioned across the chip stack. The result is a process positioned between classic two-dimensional scaling and future three-dimensional logic integration: nanosheet devices provide gate control, while backside power attacks interconnect and power-delivery bottlenecks. At VLSI 2026, TSMC’s message was that A16 is already qualified as a platform technology and moving toward production, making backside power delivery a near-term manufacturing feature rather than a distant research concept.

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Driving the Future through the “Talent Empowering Program”: Why TSMC Charity Foundation’s Youth Career Initiative Matters

Driving the Future through the “Talent Empowering Program”: Why TSMC Charity Foundation’s Youth Career Initiative Matters
by Daniel Nenni on 07-03-2026 at 10:00 am
Categories: Semiconductor, TSMC

Driving the Future through the “Talent Empowering Program” Why TSMC Charity Foundation’s Youth Career Initiative Matters

The future of work will not be shaped by technology alone. It will be shaped by whether young people are given the confidence, skills, and guidance to participate in that future. This is why the TSMC Charity Foundation’s “Technical and Vocational Talent Empowerment Program” matters. By connecting schools, industry partners, local governments, and universities, the program addresses one of the most urgent challenges facing education today: the gap between what students learn in school and what they need to succeed in real careers.

Launched through collaboration with the Hsinchu County and City Governments, Kuang-Fu High School, and Minth University of Science and Technology, the program focuses on both teachers and students. Its dual strategy is simple but powerful: help junior high school teachers provide better career guidance, while giving vocational high school students practical exposure to industry expectations. According to TSMC’s sustainability report on the initiative, the program invited 27 junior high school teachers from Hsinchu City to visit vocational education sites and learn directly from educators and automotive industry leaders.

This teacher-focused approach is especially important. Students often make early decisions about academic tracks and career pathways before they fully understand the opportunities available to them. When teachers are equipped with current industry knowledge, they can guide students more effectively and help them choose paths that match their interests, strengths, and long-term goals. This is not just career counseling; it is a form of social empowerment.

The program also gives students something that traditional classrooms often struggle to provide: hands-on experience. Through visits, demonstrations, mentorship, and exposure to departments such as automotive technology and intelligent vehicles, students gain a clearer picture of what modern technical careers look like. Industry partners including Lexus, Mazda, and Porsche-related representatives helped introduce students and teachers to hiring trends, industry-academia collaboration, and pathways from vocational education to employment.

Why does this matter? Because technical and vocational education can be a powerful engine of upward mobility. For many young people, especially those outside elite academic tracks, practical skills can become a direct route to stable employment, dignity, and long-term development. The TSMC Charity Foundation’s broader work has long included rural empowerment and employability initiatives, including career exploration videos, job fairs, and partnerships designed to help students understand real workplace possibilities.

The initiative also matters to industry. Taiwan’s economy depends heavily on advanced manufacturing, semiconductors, smart mobility, and precision technology. These sectors require not only engineers and researchers, but also skilled technicians, operators, maintenance professionals, and applied specialists. A sustainable talent pipeline cannot be built at the point of hiring alone. It must begin earlier, when students are forming their identities and imagining their futures.

At its core, the Talent Empowering Program is not simply about filling jobs. It is about helping young people see possibilities that may once have felt distant or invisible. Alumni mentorship, industry visits, and applied learning experiences allow students to connect classroom knowledge with real-world purpose. That connection can transform hesitation into confidence and uncertainty into direction.

The program’s significance also lies in its collaborative model. No single school, company, or government agency can solve the education-employment gap alone. By bringing together public institutions, vocational schools, universities, and global industry brands, the TSMC Charity Foundation demonstrates how social impact can be practical, targeted, and scalable.

Bottom line: As the Foundation continues expanding career exploration opportunities in 2026, the program offers an important lesson: investing in youth competitiveness is not charity in the narrow sense. It is an investment in social resilience, industrial sustainability, and shared prosperity. When young people are empowered to build skills, understand industries, and choose careers with confidence, they do more than prepare for the future. They help drive it.

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