Primarius 2B

Cadence/TSMC 3D

Cadence/TSMC 3D
by Paul McLellan on 06-11-2012 at 5:16 pm

Mark Twain remarked that everyone talks about the weather but nobody does anything about it. 3D ICs seems to be a bit like that. Over the last couple of years there have been lots of people talking about 3D but very little that has actually been manufactured. In addition to the weather, everyone talks about Xilinx’s 3D Virtex… Read More


A DAC Update from Mentor Graphics on IC Layout and Circuit Simulation Tools

A DAC Update from Mentor Graphics on IC Layout and Circuit Simulation Tools
by Daniel Payne on 06-11-2012 at 4:07 pm

Linda Fosler, Tom Daspit and Mitch from Mentor Graphics met with me last Monday at DAC to provide an update on IC layout and circuit simulation tools. My notes follow:

Overview – Pyxis for Schematic and Layout, IC Station is re-branded as Pyxis. (Pyxis schematic is still Falcon, Ample language is still used.)… Read More


The Apple and VMWare Alliance Threatens Microsoft (and Fabless ARM Camp)

The Apple and VMWare Alliance Threatens Microsoft (and Fabless ARM Camp)
by Ed McKernan on 06-08-2012 at 6:00 pm

The speed with which The Mobile Tsunami engulfs the old PC Market is just incredible. 18 months ago the tablet and smartphone markets were considered a Green Field of Opportunity for PC OEMs and chip suppliers to graze in for the next decade. The fences, however, are closing in fast as Apple continues to drive its iOS empire into new… Read More


Schematic, IC Layout, Clock and Timing Closure from ICScape

Schematic, IC Layout, Clock and Timing Closure from ICScape
by Daniel Payne on 06-08-2012 at 11:10 am

Before this DAC I had never even heard of ICScape, so on Monday and Wednesday I visited their booth to find out their story.

Steve Yang, Ph.D. (Co-founder and President), Ravi Ravikumar (Marketing)

ICScape was founded in 2005 in Santa Clara by Steve Yang (Circuit Design engineer for microprocessor, Synopsys) and Jason Xing (Sun… Read More


Fast Monte Carlo and Analog Fast SPICE

Fast Monte Carlo and Analog Fast SPICE
by Daniel Payne on 06-08-2012 at 10:25 am

Britto Vincent of ProPlus Design Solutions met with me at DAC on Monday morning to talk about Design For Yield (DFY) and Analog Fast SPICE.

In 2011 ProPlus announced DFY tools where the technology came from IBM, it provides fast Monte Carlo results up to 3 sigma, then added NanoSpice for faster simulation results. Similar in approach… Read More