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eSilicon on Semiconductor IP Challenges

eSilicon on Semiconductor IP Challenges
by Daniel Nenni on 03-31-2014 at 12:00 pm

On April 18, 2014 in Monterey California there will be a series of discussions on the challenges of IP reuse. These discussions are part of the 2014 Electronic Design Process Symposium (EDPS). Representatives from IP, ASIC, foundry and EDA will weigh in the challenges and issues. Here is a preview of one of the presentations from Patrick Soheili, VP & GM of IP Solutions at eSilicon.

eSilicon will provide multiple views of the problem. They are a fabless ASIC provider that helps customers design and manufacture advanced custom chips. They are also an IP provider, focusing primarily on custom memories. eSilicon will focus on IP qualification and verification.

For advanced process nodes, it’s critical that IP providers deliver fully validated technology to their customers. Beyond the obvious reasons for this (validation and verification efficiency), it is quite common for IP to be “abused” in a way or mode that was not contemplated by the developer of the IP. This fact demands a robust and complete validation technique. Aspects of the IP that need careful attention include power, clock domains, testability and physical design issues.

Design for yield is also a very important aspect of successful IP use and reuse. Addressing this issue can be quite challenging. The entire semiconductor ecosystem is involved to achieve the best power, performance or area (PPA) for a design and deliver it reliability with high yield. The IP provider needs to consider how their product will be used in a production setting. The designer (customer of the IP provider) will optimize PPA in the context of their chip design and then collaborate with the foundry to achieve the proper yield. Assembly and test are part of that equation, as is ongoing product engineering. A design-to-manufacturing co-optimization is needed.

eSilicon will also discuss the emergence of the new design hierarchy created by 2.5 and 3D technologies. These methods create a whole new series of IP reuse challenges.

Register for EDPS 2014 HERE.

About eSilicon
eSilicon, the largest independent semiconductor design and manufacturing services provider, delivers custom ICs and custom IP to OEMs, independent device manufacturers (IDMs), fabless semiconductor companies (FSCs) and wafer foundries through a fast, flexible, lower-risk path to volume production. eSilicon serves a wide variety of markets including the communications, computer, consumer and industrial segments. www.esilicon.com.

About EDPS:
The Electronic Design Processes (EDP) 2014 Symposium, in its 21th year, fostered the free exchange of ideas among the top thinkers, movers, and shakers who focus on how chips and systems are designed in the electronics industry. It provided a forum for this cross-section of the Design community to discuss state-of-the-art improvements to electronics design processes and CAD methodologies, rather than on the functions of the individual tools themselves.
www.eda.org.

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