Intel 18A vs Intel 18A-P: What Is the Difference and Why Does It Matter?Intel’s 18A process technology has become one of…Read More
WEBINAR: Why Google Cloud NetApp Volumes Matter for Modern EDA WorkloadsIn this webinar, Google Cloud and NetApp explore…Read More
How to Free Yourself from Inconsistent Engineering Documentation Before It’s Too LateEmbedded systems programs often fail because critical engineering…Read More
COMPUTEX 2026: S2C and Andes Technology Showcase Hardcore "EDA+IP" Synergy for the AI EraCOMPUTEX 2026 officially concluded under the theme “AI…Read More
The Wedding of the Year: Why AI Infrastructure Financing Is Becoming a Semiconductor StoryEvery family has that one wedding where, halfway…Read More
As you can’t have failed to notice by now, 28nm is the last process node that does not require double patterning. At 20nm and below, at least some layers require double patterning. The tightest spacing is typically not the transistors but the local interconnect and, sometimes, metal 1.
In the litho world they call double patterning… Read More
I am convinced after studying out the matter, that Aldec is one of the leaders in DO254 certification. As you listen and read the news as I do about flight MA-370, you keep theorizing and wondering. This is a good time to introduce the reader to the seriousness of flight worthy electronics and the arduous process to achieve certification.… Read More
The DSP48E2 (I do not come up with these names… Could have named it a multiplier thingy) in the Xilinx 20nm UltraScale family (I do not come up with these names… Could of named it Virtex-8, or Luke-8) is simply amazing. Today was good, as I began playing with UltraScale tools and seeing how the DSP checks out. I also encourage you to check… Read More
For those of you who missed the IEEE International Solid-State Circuits Conference last month some of the presentations are now hitting the company websites. The theme of this year’s conference was SILICON SYSTEMS BRIDGING THE CLOUD:… Read More
OK, it’s not exactly AT&T park…it’s the parking lot. But they have a huge semi loaded up with lots of cool Atmel stuff to show off some of the things that their customers are doing with their microcontrollers and display technology, primarily focused on the internet of things (IoT). I went down to check it … Read More
Started in 2002 Carbon Design Systems has ESL (Electronic System Level) modeling and validation tools for complex SoC design. With their software you can:
If you are a Mentor user, U2U, the Mentor User group is coming up on April 10th. This is an all day event at the DoubleTree. The event is free. Registration starts at 8am and the agenda itself starts at 9am. There is a reception from 5-6pm in the evening.
There are three keynotes. At 9am: Wally Rhines, CEO of Mentor. The Big Squeeze. For … Read More
By Jeff Wilson, Mentor Graphics
We’ve talked about the new requirements for Fill in IC design for advanced nodes in previous blogs on this site. This time I’d like describe the fill solution that Mentor and TSMC have jointly developed to meet the requirements of fill for TSMC’s 20nm (N20) manufacturing process.
The traditional… Read More
The annual GSA Silicon Summit is coming up in a few weeks. It is on April 10th at the Computer History Museum. Registration is at 9am and the meeting itself gets started at 9.45am. The summit finishes at 2.15pm. There are three sections during the day, and lunch is provided.
The first section is on Advancements in Nanoscale Manufacturing… Read More
Can we agree about the fact that the Moore’s law is discontinuing after 28nm technology node? This does not mean that the development of new Silicon technology, like 14nm or beyond, or/and new Transistor architecture like FinFET will not happen. There will be a market demand for chips developed on such advanced technologies: mobile… Read More
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Intel 18A vs Intel 18A-P: What Is the Difference and Why Does It Matter?