The Accidental Infrastructure: How Crypto Miners Built the Foundation of the AI BoomMost crypto forty-niners died broke in a warehouse…Read More
From Detection to Safety: Reframing Fault Simulation for Functional SafetyIn the early 1980s, when computer-aided engineering (CAE),…Read More
Driving the Future through the “Talent Empowering Program”: Why TSMC Charity Foundation’s Youth Career Initiative MattersThe future of work will not be shaped…Read More
Foundation IP for Intel 18A: Technical Overview and Why It MattersSynopsys Foundation IP for Intel 18A is a…Read More
WEBINAR: Defacto is Boosting Front-end SoC Design With AI-Powered EDA toolsThe real promise of AI in EDA is…Read More
Cadence announced their 2Q results this afternoon. I listened to the conference call.
You can read all the details of the results in the press release but the big picture is:
While listening to the Intel and AMD conference calls last week I was reminded of the ATI acquisition by AMD and the painfully long cultural assimilation that ensued. The title of this blog could just as easily have been “Custom vs Synthesizable Design Cultures” or “The Real Reason Why AMD is Fabless” because that is closer to how … Read More
The reliability metric, Mean Time Between Failures (MTBF), is often misunderstood. Use of an MTBF metric generally assumes a random failure process, one that is very infrequent and has no memory of past failures. Such failure modes can occur in System-on-Chip (SoC) designs and include radiation effects, synchronizer malfunctions… Read More
I recently published an article on Semiwiki “Is SOI Really Less Expensive”. That article was the result of months of careful research and analysis. I looked at planar FDSOI versus bulk planar, bulk FinFETs and FinFETs on SOI at three different nodes. I took a consistent set of assumptions with respect to the fab used to run the processes,… Read More
FPGAs in many ways are still a bit mysterious to some folk. I was at a high level summit in April, and I realized that many there had no idea what an FPGA was. They knew at least what a CPU was or meant and that their kids talk about GPUs. A good analogy I have for an FPGA when compared to a CPU is something like this. Think of the FPGA and CPU as … Read More
Rather than watch the World Cup battle for third place, my beautiful wife and I spent last Saturday afternoon at the CASPA Wearables Symposium. The most interesting presentation was from Samsung because it included slides on their foundry offering. In regards to wearables, I still don’t see the ROI I need to buy one, yet. We are getting… Read More
I spent all of last week at SEMICON West meeting with customers, potential customers, partners and various industry analysts and experts. I was involved in many interesting discussions over the course of the week and I thought I would share some of the more interesting observations:
Alternate Fin Materials Pushed Out
I have for… Read More
One of Coventor’s flagship products is SEMulator3D, and at Semicon West they announced a new version, 2014.100.
SEMulator3D is a powerful 3D semiconductor and MEMS process modeling platform. It uses highly efficient physics-driven voxel modeling technology. It models the physical effects of process steps, which is… Read More
The most interesting part of the semiconductor market for me has always been the Custom Chip sector – the FPGA, ASIC and SoC companies where I have spent my entire career. These three segments provide an excellent barometer of the overall state of financial health and technological innovation for the entire High Tech industry, … Read More
Earlier in the week, eSilicon and IDT announced a collaboration to accelerate development of next-generation RapidIO switches. These are used to meet the higher performance demands required for new wireless, embedded and computing infrastructures. The two companies will initially work together to develop RapidIO switches… Read More
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The Packaging PDK Is the Missing Layer for Co-Packaged Optics