MIPI SoundWire specification will be integrated into mobiles systems, like smartphone or media tablet. In fact some of the well-known chip makers have already decided to integrate MIPI SoundWire into their last application processor release. MIPI SoundWire is also the type of specification which could be used in many other applications even if the primary target is smartphone, features phones and media tablet. According with Cadence: “SoundWire is a new digital audio interface specification from the MIPI Alliance that enables bi-directional digital communication with a focus on low complexity and low gate count, making it attractive to many mobile design applications.” The important words are low complexity and low gate count. An application processor for mobile count billion transistors, so the gate count is not an issue, but if we consider the IC devices controlling the peripheral (earpiece, speaker, internal micro, etc.), these are probably designed in more mature technologies, up to 130nm or even more. Such chips are targeting consumer or mobile applications, implying very high production volume and the cost is a key driver. Thus, benefiting from an efficient interface protocol is attractive at the condition that the cost impact is kept as low as possible.
MIPI SoundWire Controller IP is master/slave interface protocol. The master register can be accessed internally from a 32-bit AHB client interface. All registers are mapped to host memory space. Certain timing critical registers are banked to allow synchronous switching without interruption to data streams. We understand from the system level block diagram above pictured that the master could be either integrated in the application processor (mobile system), either in a DSP based audio ASSP. Both types of chips integrate a processor, so the choice of an AMBA AHB bus to access the master is judicious. The Slave Controller IP contains only a small subset of the logic.
MIPI SoundWire is Feature-rich IP solution: it was important to offer high level of configurability. In fact, the master can be configured with the following options:
- PDI count and width
- PDI type
- PDI FIFO depth
- Command FIFO depth
- Data lane count
- Source input clocks
MIPI SoundWire is a layered interface protocol, and the physical layer definition is an important part of the specification. MIPI SoundWire protocol doesn’t use MIPI D-PHY or even C-PHY, but the PHY uses modified NRZI. The PHY logic drives or detects multi-lane capable SoundWire IO interface. The master controller contains a clock generator that drives the clock signal to all slaves. The clock frequency is derived using a configurable gear box and a reference clock input. Clock stop handshake protocol is supported by the PHY layer. Clock can be stopped and resumed with precise synchronization to SSP interval. Once clock is stopped, the master controller enables asynchronous slave or self wakeup detection.
“With a complete solution targeted specifically for MIPI SoundWire, including verification IP released in March, we are fully enabling designers to integrate the latest technologies into their SoC designs for the mobile and consumer market” said Martin Lund, senior vice president of the IP Group at Cadence. Providing the related verification IP should facilitate early adoption of the new SoundWire spec. In fact, Cadence is a longtime supporter of MIPI specifications, as in the early days of the MIPI Alliance, the company was offering Verification IP for the various MIPI specification like DSI or CSI-2. The release of MIPI SoundWire Verification IP well in advance (March 2014) and Design IP now is a clear sign that Cadence send to the competition: Cadence has invested a lot to develop IP supporting MIPI specifications and the company will be present on this front.Share this post via: