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At the TSMC Technology Symposium last month Suk Lee presented a lot of information on design enablement. Suk is an interesting guy with a unique background in ASIC, Semiconductor, EDA, and now Foundry. In baseball terms that would be like playing infield, outfield, home plate, and umpire!
Around the turn of the millennium Suk actually… Read More
One of the advantages of being an independent consultant is that I get to choose who I work with and what type of projects I accept. In fact, that is why I originally started blogging, to get exposure to a wide range of topics and brand myself as a strategic semiconductor business development professional. Now rather than wasting time… Read More
Let me precise that by “IoT” I think about the IoT devices market, made of hundreds of application, wearable gadget to medical, home automation, and so on. One direct consequence of IoT (device) market explosion will be the strong growth of the server market (cloud), to transfer, compute and store information generated by the billions… Read More
I have been observing Fractal Technologiesexhibiting at DACyear after year, and every year they have demonstrated good value added features in their tools for SoC and IP development. This year at 52[SUP]nd[/SUP] DAC Fractal’s booth number is 1110. Earlier in this year Fractal had added a new ‘Cdiff’ feature in its flagship product… Read More
From May 3[SUP]rd[/SUP] to May 6[SUP]th[/SUP] the 26[SUP]th[/SUP] annual Advanced Semiconductor Manufacturing Conference (ASMC) will be held in Saratoga Springs, New York.
The ASMC offers a unique view of challenges to the semiconductor industry focusing on things like defect reduction, metrology and fab operations. In… Read More
Digital IC design has been largely automated with high-level languages, RTL coding, logic synthesis, and automated place and route tools. What about analog IC layout automation, is it possible? A few EDA companies think that it is possible and even practical. In recent memory there were two companies really focused on analog … Read More
A year ago many eulogized the death of Moore’s Law at 28nm due to higher prices per transistor at more advanced nodes, but now that we have celebrated the 50th anniversary let’s look ahead to technology scaling and electronic systems miniaturization for the next decade. Despite our industry’s bipolar tendencies and daunting technical… Read More
It’s all about Cost of Ownership (CoO) and system level integration. If you target automotive related application, like audio or video processing or control of systems (Motor control, Inverter…) you need to integrate strong performance capable MCU with a DSP. In fact if you expect your system to support Audio Video Bridging (AVB)… Read More
Timing closure is a “tortoise” for some system-on-chip (SoC) designers just the way many digital guys call RF design a “black art”. Chip designers often tell horror stories of doing up to 20 back-end physical synthesis place & route (SP&R) iterations with each iteration taking a week or more. “Timing closure”, a largely… Read More
One of the trickiest tasks in designing a modern SoC is getting the clock tree(s) right. The two big reasons for this:
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Rapidus, IBM, and the Billion-Dollar Silicon Sovereignty Bet