The Electronic Design Processes (EDP) 2016 Workshop and Symposium, in its 23rd year, has fostered the free exchange of ideas among the top thinkers, movers, and shakers who focus on how chips and systems are designed in the electronics industry. It has provided a forum for this cross-section of the design community to discuss state-of-the-art… Read More
Customized Foundation IP Enables the Next Generation of Automotive ComputeAs vehicles become increasingly software-defined, automotive semiconductor suppliers…Read More
Rambus Delivers Complete DDR5 Client Chipset for High-Speed CUDIMM and CSODIMM Memory ModulesThe rapid emergence of AI-enabled personal computers is…Read More
From Evidence to Authority: Bounded Gate Authority for Governed Semiconductor RealizationAdvanced semiconductor systems are no longer limited by…Read More
Synopsys and Samsung Foundry Extend AI-Driven Design Collaboration for Advanced 2nm and Multi-Die SystemsAt SAFE Forum 2026, Synopsys announced significant advancements…Read More
Broadcom Told the Truth. The Market Hasn’t Heard the Rest of It Yet.Hock Tan and his CFO Kirsten Spears logged…Read More
Debugging is the whole point of prototyping
The prototype is obviously the end goal of FPGA-based prototyping, however success of the journey relies on how quickly defects can be found and rectified. Winning in the debug phase involves a combination of methodology, capability, and planning. Synopsys recently aired a webinar on their HAPS environment and its debug ecosystem.… Read More
Singularity, Semiconductors and Software
One of my all-time favorite movies is 2001 A Space Odyssey where one of the leading roles is an AI-based system aboard a spacecraft named Hal that is designed to be a perfect machine yet makes a mistake and then cascades into assaulting and eliminating the human crew members. The future time when semiconductors and software combine… Read More
A CIA Perspective on Privacy and Security
It may seem odd to look to the CIA for viewpoints in this area but in in many ways they are just as concerned as we are. After all, in aggregate, widespread identity theft and hacking both internally and by foreign nationals, theft, electronic ransom and other illicit acts are as much a threat to the security of the country as they are … Read More
Join the Multi-die IC session on April 21 at EDPS 2016 in Monterey, CA
Following Moore’s Law down to 10 or even 7 nm labeled feature size demands US $ hundreds of millions of up-front investment, a very large design team and two or more years of development time. These parameters suggest that it only makes sense for very high volume applications to continue on the shrink path to increase SoCs’ functionalities.… Read More
EDAC Name Changing for ESDA, but what about IP ?
The EDA Consortium (EDAC) has changed name for Electronic Systems Design Alliance (ESD Alliance). That’s a good reminder that IC are developed (thanks to Design Automation) to be integrated into a System. A wide design ecosystem support system development, including embedded software, design intellectual property (IP), … Read More
Self-contained low power Wi-Fi IP for IoT apps
The emerging theme of fit-for-purpose IoT parts gained yet another perspective, this time with ARM and CEVA chiming in on a low-power Wi-Fi approach outlined in a new webinar. It was a rather unique event with an abbreviated 25-minute presentation and an extended 35-minute Q&A that added a lot of insight.… Read More
Wearables Mean Continuous Growth in the Internet of Things Ecosystem
The Internet of Things encompasses a wide range of connected services, technologies, and hardware devices. Yet, for consumers, it is the growing number of portable and wearable devices that will be their main interface with IOT tech. The wearable device market is rapidly evolving, especially when it comes to smart watches and… Read More
“Thinking Outside the Chip”
While pushing Moore’s Law’s boundaries in the world of 2D packaging, companies are starting to explore nontraditional approaches towards designing integrated circuit chips. 2D packaging is currently the most used method in designing chips in the industry, and while it leads in efficiency of power and performance, it lacks … Read More
EUV is coming but will we need it?
I have written multiple articles about this year’s SPIE Advanced Lithography Conference describing all of the progress EUV has made in the last year. Source power is improving, photoresists are getting faster, prototype pellicles are in testing, multiple sites around the world are exposing wafers by the thousands and more. … Read More
Intel: Pushing EMIB Forward: Design Methodology Insights with Synopsys Tools