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IMEC Technology Forum (ITF) – Secrets of Semiconductor Scaling

IMEC Technology Forum (ITF) – Secrets of Semiconductor Scaling
by Scotten Jones on 06-07-2016 at 4:00 pm

 IMEC is a technology research center located in Belgium that is one of the premier semiconductor research centers in the world today. The IMEC Technology Forum (ITF) is a two-day event attended by approximately 1,000 people to showcase the work done by IMEC and their partners.

An Steegen is the Senior Vice President of Process Technology at IMEC. An was part of a panel discussion during the “Scaling is dead. Long live scaling” session, she then delivered a keynote presentation entitled Secrets of Semiconductor Scaling and finally I had the opportunity to interview her. In this blog I will discuss An’s presentation and my follow up interview. I will blog about the panel discussion separately. I will start with An’s keynote and then discuss our interview.

Secrets of Scaling Presentation
The data traffic explosion is driving infrastructure for Internet Of Things (IOT) and that drives a need for CPU power and storage capacity. Phones and IOT devices will both need it. The drivers are still in place for the industry.

Happy CPU scaling gave 2x the number of transistors and constant power density. But transistor and voltage scaling are no longer in-line and that leads to not being able to turn on all of the transistors (dark silicon).

Near term technology is driven by lithography and materials design.

EUV for critical half pitch simplifies the process. EUV can print 7nm requirements as a single pattern. 10nm to 7nm to get a 50% die cost reduction we need EUV and a transition from 9 track to 6 track design with self-aligned processes and buried rails.

FinFET from 28nm to 14nm looked great. 14nm to 10nm also gets a 20% performance improvement and 40% power improvement. 7nm may be an issue. They are looking at horizontal nanowire and can get a 30% performance boost and 50% power improvement at 5nm.

Looking at the ultimate limit for FinFETs and alternate materials, germanium is better at 0.5 volts. Nanowire have better electrostatics than FinFETs at 5nm. For interconnect we will see copper extensions and then cobalt and ruthenium. We will see cobalt filled vias near term. They believe they have a Back End Of Line (BEOL) path for the next several nodes.

Using STT MRAM in place of SRAM for cache can give 4x scaling (STT MRAM can be fabricated over the logic in the metal layers). There is a lot of work being done on 20nm MRAM and low current switching MRAM. MRAM can replace SRAM for on-chip cache and if the density gets there eventually replace DRAM.

Vertical FETs, complementary FETs (NMOS over PMOS horizontal nanowires) and stacked FETs can all drive more performance. Wafer to wafer bonding of heterogeneous wafers can reduce wiring and power by 50%. Beyond 2D CMOS spin wave has low energy but is slow. Tunneling devices can be fast and low energy.

In Von Neumann system there is a gap between DRAM and NAND performance. You can fill the gap with storage class memory. For 3D NAND they are working on stress management of multiple layers, III-V channels and making stacks shorter.

To improve bandwidth use 3D technology for wide I/O, scale to very small TSV and micro bumps with smart interposers. Silicon photonics on interposers for >1TB/sec/mm.

We need to rethink system architecture. Use resistance elements to do neuromorphic computing. They have already seen islands of unhappy scaling but we have always gotten out of them.

An Steegen interview
To start the interview, I set the stage by saying I wanted to discuss the following:

  • FinFETs – how far do they scale.
  • Interconnect issues and scaling.
  • Contact resistance.
  • Horizontal nanowires, when?
  • DRAM is slowing, what’s next?
  • EUV first uses, when and what?
  • 3D NAND Challenges
  • 3D XPoint scaling

One thing I really enjoyed about interviewing An was that once I set the stage with my questions she was off and running with a lot of great information about each question.

For logic the first question for FinFETs is what is 10nm and 7nm. Her presentation was based on full 0.7x scaling. 28nm to 14nm FinFET gave a tremendous performance benefit. No problems with dimensional scaling from 14nm to 10nm. For performance you need to optimize contact resistance and the k value of devices spacers plus strain engineering. At 7nm ideal scaling becomes an issue. Dimensional scaling squeezes down to a 5nm fin width and a 45nm fin height. You can’t scale anymore, height no gains due to parasitics and can’t scale width below 5nm. Need to get performance from performance boosters, contact resistance is at 1e-9, need an order of magnitude better at 7nm. Does 7nm become just a speed push or do you scale dimensionally and insert EUV where there isn’t too much disruption. You can insert EUV for metal and vias, you can get 2D metal with a single exposure, they are getting data today at 34-35nm pitches. For 1D metal use SAQP with EUV for blocks to replace 4 color blocks with single blocks and single pass vias.

EUV dose, resolution and LER needs to be optimized. They want a resolution of 30-32nm full pitch and good LER. The best resists have acceptable resolution but LER is too high. Shot noise is one problem for LER but not the whole story. Post treatment line smoothing with depositions and etches can be used. She doesn’t see LER as a show stopper! They don’t want to introduce too many things at one time so try to introduce EUV at 7nm before transitioning to a new transistor type. Metal will be 3 color at 10nm. Focus on EUV and introduce at 7nm to replace 4 color metals.

For 5nm she is very hopeful about nanowires or nanosheets or a combination. Both are more confined than FinFETs. They prefer a horizontal solution because it is a migration of a FinFET process flow. Nanowires are better than FinFETs at 7nm and can migrate. She thinks nanowires have a 2 node lifetime. If you don’t get EUV in at 7nm you have to do it at 5nm along with nanowires and that is too much.

For high mobility channels Silicon Germanium (SiGe) is looking good for PFETs, they have proof points that at low Vt they outperform silicon (Si). The question is how do you implement them so that you can have low Vt and high Vt for System On a Chip (SOC). You can potentially have Germanium (Ge), Si and Indium Gallium Arsenide (InGaAs) all on the same chip. Today SiGe for PMOS looks good, they have an InGaAs proof point, Ge for NMOS is tricky with dielectric issues. Ge could be a FinFET booster if ready or maybe come in for nanowire. She thinks SiGe could be ready for a FinFET node. For nanowires it is a FinFET derivative and you need SiGe anyway for etching out nanowires.

For interconnect the resistance is a function of wire length and resistivity. As you shrink nodes the length shrinks. She thinks we will see cobalt vias and contacts at 10nm cobalt metal liners. Think cobalt vias and contact stay in for 7nm.

DRAM scaling is still happening but is slowing down. EUV would be a benefit. Many options have been explored for capacitors, double trench and other materials. You need physical and electrical thickness and they go hand in hand. Physical thickness has been pushed and there isn’t much room in the capacitor. You can optimize the periphery to manage a lower capacitance by providing lower parasitics or more drive current. FinFETs, HKMG and improved metals all help. Long term STT MRAM with a 4F2 cell could replace DRAM. They are seeing good progress and are seeing 20nm today (40nm pitch). A multilevel STT MRAM may be a solution. STT MRAM for IOT cache replacement could happen within the next 2 years, DRAM replacement by STT MRAM is likely after 2020.

3D NAND stress management is a key challenge, you need to keep the wafer flat. They are working on a lot of stress models and how to mitigate and align if you have to. The number of layers you can pattern is hard mask and etch constrained. You need to optimize the devices to shrink thickness, scale gate length and dielectric. Eventually you need to go to stack on stack where you deposit a set of layers and pattern them and then deposit and pattern a second set of layers (I recently heard Intel-Micron are doing this for their 64-layer device). Another issue is will your device behave the same at the top and bottom of the stack. Today the channel is polysilicon and eventually you will need higher channel mobility. The channel is also currently a “macaroni” channel and eventually you may need a solid channel. Stack on stack depends on stress engineering and how good your etch is. We may see stack on stack at 64 layers (32 on 32) although she was more expecting 128 layers (64 on 64). High mobility channels the sooner it happens the better. Putting CMOS under the stack helps with density but adds more stress.

Storage Class Memory (SCM), do shrinks and stack, she sees a heavy push here. The Intel-Micron 3D XPoint part is 2 layers at 2xnm, what is next, 2xnm with 4 layers or 1xnm with 2 or 4 layers. How does the device behave as you scale to dimensions? For Phase Change Memory (PCM) you need a lot of current and can the selector drive the current. Depending on the cell you use current may or may not scale, PCM may scale but RRAM may not because it is filamentary.

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