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Ford Prioritizes Safety; Revolutionizes ConnectivityFord Motor Company’s debt may have been downgraded…Read More

Tcling Your Way to Low Power VerificationOK – maybe that sounds a little weird,…Read More

GM's Dashboard SurrenderThere was a time when General Motors’ OnStar…Read More

AI Chip Prototyping PlanI recently had the opportunity to sit down…Read More

For EDA Users: The Cloud Should Not Be Just a Compute FarmWhen EDA users first started considering using cloud…Read More

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October 14, 2010

Why Only MV When You Can MC, MM & MV?

Why Only MV When You Can MC, MM & MV?
by glforte on 10-14-2010 at 4:14 pm
Categories: EDA, Mentor, a Siemens Business

Resistance is futile. I recently caved and switched to an iPhone after having been a loyal Google phone user for more than year. Apart from the coolness factor, my main motivation was corporate mail support that was absent in Gphone, plus the fact that I got the iPhone for free when my wife upgraded hers. The difference is day and night… Read More

October 14, 2010

How to Multi-Voltage IC Design in 10 Easy Steps

How to Multi-Voltage IC Design in 10 Easy Steps
by glforte on 10-14-2010 at 4:14 pm
Categories: EDA, Mentor, a Siemens Business

What I’m really describing here is an over-simplified backend flow for physical design of low power ICs with multiple voltage domains. If you haven’t ventured into this territory yet, this will hopefully give you some food for thought. Here are the basic steps:… Read More

October 14, 2010

So, Why Not Just Write Better Rules?

So, Why Not Just Write Better Rules?
by glforte on 10-14-2010 at 4:00 pm
Categories: EDA, Foundries, Mentor, a Siemens Business, TSMC

In my submission about TSMC making some DFM analysis steps mandatory at 45nm (see “TSMC’s DFM Announcement”), I ended with a question about why the foundries can’t just write better design rules (and rule decks) to make sure all designs yield well. Here’s my take on this complicated question.… Read More

October 14, 2010

TSMC’s DFM Announcement

TSMC’s DFM Announcement
by glforte on 10-14-2010 at 4:00 pm
Categories: EDA, Foundries, Mentor, a Siemens Business, TSMC

If you are a TSMC customer, no doubt you have heard TSMC is requiring lithography and planarity analysis for all 45nm designs. Their website says customers can either run it themselves, or contract TSMC services to do it. The most cost-effective way would be for the customers to run it themselves, but some might not have the resources… Read More

October 14, 2010

I finally got to watch the critically acclaimed sci-fi movie “Inception” last weekend and life has not been the same since. Without giving away too much detail for the benefit of those who have not watched it yet, the main plot involves dreams within dreams within dreams – three levels to be precise—to “incept” an idea into … Read More

October 13, 2010June 14, 2019

Semiconductor Manufacturing International Corporation 2010

Semiconductor Manufacturing International Corporation 2010
by Daniel Nenni on 10-13-2010 at 11:01 pm
Categories: Uncategorized

In celebrating the 10th anniversary of SMIC, CEO David Wang ushers in a new era of China semiconductor manufacturing with triumphs versus promises. By triumphs David means profits, which SMIC saw for the first time in Q2 2010. The future looks even brighter for SMIC as the China semiconductor demand versus supply gap is an estimated… Read More

October 10, 2010June 14, 2019

TSMC OIP Conference 2010 Critique!

TSMC OIP Conference 2010 Critique!
by Daniel Nenni on 10-10-2010 at 10:18 pm
Categories: EDA, Foundries, TSMC

Okay, this is more of a, “What I would do if I was TSMC” than a critique, but I needed a one word descriptor for the title. This was the third TSMC OIP Conference and I would guess about 250 people attended. This was the first time I have seen TSMC in “reactive” mode versus “proactive” leadership mode, so I was a bit disappointed. TSMC is … Read More

October 8, 2010

Critical Area Analysis and Memory Redundancy

Critical Area Analysis and Memory Redundancy
by SStalnaker on 10-08-2010 at 8:08 pm
Categories: EDA, Mentor, a Siemens Business

Simon Favre, one of our Calibre Technical Marketing Engineers, presented a paper on Critical Area Analysis and Memory Redundancy at the 2010 IEEE North Atlantic Test Workshop in Hopewell Junction, NY, just up the road from Fishkill. As Simon says…

Fishkill, New York. IBM is in Fishkill. IBM invented Critical Area Analysis in what,… Read More

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Reusing Your IPs & PDKs Successfully With Cadence® Virtuoso® Taiwan ESD Workshop Recording Reduce Risk and Improve Quality of AMS IP’s using AI-Powered Automated Timing Arc Prediction Finding Your Way Through Verification (Text) REPLAY: GPU-Powered SPICE: The Way Forward for Analog Simulation REPLAY: Avoiding CDM (Charged Device Model) ESD Failures REPLAY: eFPGA – "What a great idea! But I have no idea how I’d use it!" REPLAY: Ensuring System-level Security Through Hardware/Software Security Verification REPLAY: Fabless: The Transformation of the Semiconductor Industry REPLAY: The Brave New World of Customized Memory REPLAY: Embedded FPGA: The Fabric for Optimized Machine Learning REPLAY: VLSI Design Methodology Development REPLAY: Lightspeed Data Sync - Design Workspace Problems Solved! REPLAY: Desinging Complex SoCs and Dealing with Multiple File Formats? REPLAY: How ASIC/SoC Prototyping Solutions Can Help You! [filter] => 1 [visual] => 1 [rw_opt] => Array ( [widget_select] => 1 [others_front_page] => 1 [category_96] => 1 [category_6435] => 1 [category_95] => 1 [category_157] => 1 [category_50] => 1 [category_13] => 1 [category_90] => 1 [category_89] => 1 [category_3611] => 1 [category_178] => 1 [category_14418] => 1 [category_51] => 1 [category_97] => 1 [cpt_page] => 1 [others_blog_page] => 1 [category_44] => 1 [category_5] => 1 [category_32] => 1 [category_22] => 1 ) [display_widget_mobile] => 1 )

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SemiWiki

Why Only MV When You Can MC, MM & MV?

How to Multi-Voltage IC Design in 10 Easy Steps

So, Why Not Just Write Better Rules?

TSMC’s DFM Announcement

So, Why Not Just Write Better Rules?

TSMC’s DFM Announcement

Effects of Inception

Semiconductor Manufacturing International Corporation 2010

TSMC OIP Conference 2010 Critique!

Critical Area Analysis and Memory Redundancy

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