DVCon Banner 2020 SemiWiki

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                    [post_date] => 2011-08-17 19:18:00
                    [post_date_gmt] => 2011-08-17 19:18:00
                    [post_content] =>  When you think of Indian music you might think of ragas for the sitar. But when you think of Indian MUSIC, that is the Magma user group meeting (Magma Users Summit for Integrated Circuits) coming up on September 7th in Bangalore (note: the date has changed from when it was originally announced). It is at Vivanta by Taj on M G Road.

There is a guest keynote by Balajee Sowrirajan of Texas Instruments OMAP business unit on Trends and challenges in designinbg wireless application processor--what is the need of the day? at 9.30am.

The second keynotet is at 12.35pm, just before lunch, by Rajeev Madhavan, Magma's CEO.

There are other presentations by TI, Qualcomm, ARM, Netlogic, Microchip and Silicon One.

More information, including the complete agenda, is here.

To register, go here.

[post_title] => MUSIC in Bangalore [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => music-in-bangalore [to_ping] => [pinged] => [post_modified] => 2019-06-14 21:39:53 [post_modified_gmt] => 2019-06-15 02:39:53 [post_content_filtered] => [post_parent] => 0 [guid] => https://35.226.139.164/uncategorized/716-music-in-bangalore/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [1] => WP_Post Object ( [ID] => 713 [post_author] => 9491 [post_date] => 2011-08-17 17:24:00 [post_date_gmt] => 2011-08-17 17:24:00 [post_content] =>  Atrenta has four seminars coming up on SoC realization. More and more design is actually about finding IP and integrating it together at the block level, and then handing it off to a standard RTL to GDSII flow. The three focus areas are:

  • finding quality IP faster
  • accelerating IP integration and SoC assembly
  • handing off RTL successfully.

The seminars are at:

To register, click on the city name above for the location that you want to attend. And if you fill out your survey at the end of the event you could win an iPad.




 [post_title] => Fast Track your SoC Design [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => fast-track-your-soc-design [to_ping] => [pinged] => [post_modified] => 2019-06-14 21:39:53 [post_modified_gmt] => 2019-06-15 02:39:53 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/fast-track-your-soc-design.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [2] => WP_Post Object ( [ID] => 712 [post_author] => 9491 [post_date] => 2011-08-17 15:15:00 [post_date_gmt] => 2011-08-17 15:15:00 [post_content] =>  Next Tuesday, August 23rd, is the ANSYS Regional Conference for Silicon Valley. It takes place at the Techmart Network Meeting Center. Apache has three presentations during the day:


  • 9.25-9.45 Andrew Yang Introducing Apache Design Solutions
  • 11.00-11.30 Methodology for delivering power-efficient designs from concept to silicon
  • 1.30-2.00 Utilizing chip macro modeling for chip-package-system simulation.

The conference is free. A detailed agenda for the whole day is here.

Register here.

Details on ANSYS regional conferences for other regions are here.

[post_title] => ANSYS Regional Conference [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => ansys-regional-conference [to_ping] => [pinged] => [post_modified] => 2019-06-14 20:53:02 [post_modified_gmt] => 2019-06-15 01:53:02 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/ansys-regional-conference.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [3] => WP_Post Object ( [ID] => 711 [post_author] => 20367 [post_date] => 2011-08-17 01:00:00 [post_date_gmt] => 2011-08-17 01:00:00 [post_content] => Mr. TTL (otherwise known as Texas Instruments or TI) has had a great run in the cellular market but it is time to decamp. The future is Analog and OMAP must depart to one of the remaining players looking to win the Smartphone and Tablet market. TI is exiting the market so it can focus on the high volume analog market.

On first sight, the Google acquisition of Motorola should seem to bolster TI since they are a big user of OMAPs. The new OMAP 5 architecture looks to be very impressive in terms of increased performance at reduced power over ARM9 competitors and is the basis for Ice Cream, the next version of Google’s Android O/S. So why leave the party as things are looking up? The short answer is that Analog can be a 70% Gross Margin Business and the ARM processor market is headed for major price compression.

During the last downturn, Rich Templeton decided that enough is enough. TI, a company that prides itself on always having a big Fab in Dallas, decided to move forward on building and outfitting the world’s first 300mm Analog fab. TI would build in volume and sell at competitive pricing that still left lots of room for margin. The acquisition of National, their low cost competitor completed the plan. Think of TI as in the same spot Walmart would be if it acquired Target and Costco. Of course if you aren’t the Walmart or TI type of shopper, you can always go to Linear Tech to get your high priced, custom analog.

To fill the big 300mm fab and generate high growth, Templeton has to get rid of OMAP. It is, in the eyes of Intel and Apple, a competitor and if TI wants to own the Analog world it must not compete with the big Processor Players. You could say the same about nVidia, Qualcomm, Broadcom and Marvell. A little history in order here, back in 1997 Brian Halla had dreams of conquering the world with cheap PCs. So he bought Cyrix. Intel congratulated him by redesigning their reference boards sans National analog. A major Migraine swept through the sales ranks over at National’s Headquarters.

But who would want OMAP? The current darlings of the ARM world are Qualcomm and nVidia. Broadcom and Marvell are lagging and AMD has yet to figure out it needs an ARM core to marry with x86. But of the three Broadcom has the cash and its core businesses are doing exceptionally well. Wireless is a major strength. The weakness is in application processors. Without both a strong baseband and application processor, the long-term outcome is iffy.

If Broadcom acquires OMAP they have a share of the business with nVidia in the Android market, including Motorola. A huge step up from where they are today. However, within all this, one gets the sense that more tremors are on the way and the price to play the next round will go up another notch.

Note: You must be logged in to read/write comments



 [post_title] => Mr. TTL’s Future is Analog: Time to Sell OMAP to Broadcom [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => mr-ttls-future-is-analog-time-to-sell-omap-to-broadcom [to_ping] => [pinged] => [post_modified] => 2019-06-14 21:39:52 [post_modified_gmt] => 2019-06-15 02:39:52 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/mr-ttls-future-is-analog-time-to-sell-omap-to-broadcom.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [4] => WP_Post Object ( [ID] => 707 [post_author] => 20367 [post_date] => 2011-08-16 20:00:00 [post_date_gmt] => 2011-08-16 20:00:00 [post_content] =>  Call me Ishmael. Some years ago –in the mid 1990s – having little or no money in my purse and nothing particular to interest me on shore, I thought I would sail the startup ship Cyrix and see the watery part of the PC world. Whenever I find myself grim about the mouth or pause before coffin warehouses, and bring up the rear of every funeral I meet – I think back to the last words that came from Captain Ahab before the great Moby Dick took him under: “Boy tell them to build me a bigger boat!”

You see the great Moby Dick is just not any whale, it is the $55B great white sperm whale that has been harpooned many of times and taken many a captain Ahabs to the bottom of the ocean. It still lives out there unassailable, despite the ramblings of the many new, shiny ARM boats docked on Nantucket Island, a favorite vacation spot of mine from my youth.

Perhaps there could be a great whaling ship constructed out of the battered wood and sails of the H.M.S. nVidia and the H.M.S. AMD. Because the alternative is that they must go down separately. Patience wears thin for ATIC (Advance Technology Investment Company), the Abu Dhabi investment firm that has poured billions of dollars into Global Foundries and AMD with the hope of being the long term survivor in the increasingly costly Semiconductor Wars. To be successful, the company needs a fab driver larger than what nVidia and AMD represent separately.

Jen Hsun Huang is the most successful CEO to ever challenge Intel in the PC ecosystem and yet he is not strong enough to overcome the Moore’s Law steamroller that naturally seeks to integrate all the functions of a PC into one chip. Both AMD and Intel have integrated chipsets and “good enough” graphics into their CPU thus limiting his leading revenue generator. He made a strategic move with Tegra to get out in front of the more mobile platforms known as Smartphones and Tablets but they may not ramp fast enough to allow him to make it to the other side of the chasm.

AMD, has pursued Intel forever but now is without a leader that can stop the carnage of a strategy that seeks to be Intel’s me too kid brother. It bleeds with every CPU sold to the sub $500 market. Lately, Intel has been on allocation and given them a profitable reprieve, but don’t count on it lasting forever as Intel eventually moves to the next node and adds more capacity.

There are huge both short term and long term benefits should Jen Hsun decide to merge with AMD. In the short term, nVidia and AMD are in a graphics price war where the AMD sales guy tells the purchasing exec “whatever nvidia bids mark me down for 10% less and see you at the golf links at 4 o’clock.” They have lost key sockets in Apple’s product line as well as other vendors. Merging with AMD raises revenue and earnings in an instant. The merged company would eliminate the duplicate graphics and operations groups.

Next, nVidia could implement the ARM+x86 multicore product strategy for the ultrabook market that I outlined in: Will AMD Crash Intel’s $300M Ultrabook Party? . The market offers high growth, ASPs and margins and is a close cousin of the tablet which nVidia is already targeting with Tegra.

Third, nVidia has made traction in the High Performance Computing (HPC) Market with Tesla. But don’t get confused with HPC = Data Center Servers. The Data Center runs x86 all the time. Intel has a $10B+ business going to $20B in the next 3 years. They are raising prices at will with no competition in sight. nVidia and AMD could team up to offer customers an alternative platform with performance and power tradeoffs between x86 and Tesla.

The icing on the cake is that this can all be financed by ATIC. Back in January when Dirk Meyer was let go as CEO of AMD and the stock was $9, I speculated to a semiconductor analyst that AMD would be bought when it went under $5. Why $5, it’s psychological. The wherewithal to do this is in ATIC’s hands but they have little time to spare.

ATIC owns 15% of AMD and 87% of Global Foundry. Today nVidia is worth $8B and AMD is worth $4.2B. Combined they would be worth significantly more than $12B because the graphics competition would end and the joint marketing and manufacturing operations would consolidate. It is logical for ATIC to take a 20% ownership in nVidia and finance the rest of the purchase in any number of ways. Back in the DRAM downturn of the 1980s, IBM bought a 20% stake in Intel to guarantee they would be around until the 386 hit the market.

Now that the ECB and the Fed have lowered interest rates to 0% and have the printing presses running overtime, why wouldn’t ATIC finance the new H.M.S. Take- No-Prisoners.



 [post_title] => Captain Ahab Calls Out for the Merger of nVidia and AMD [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => captain-ahab-calls-out-for-the-merger-of-nvidia-and-amd [to_ping] => [pinged] => [post_modified] => 2019-06-14 21:39:51 [post_modified_gmt] => 2019-06-15 02:39:51 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/captain-ahab-calls-out-for-the-merger-of-nvidia-and-amd.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [5] => WP_Post Object ( [ID] => 710 [post_author] => 3 [post_date] => 2011-08-15 19:11:00 [post_date_gmt] => 2011-08-15 19:11:00 [post_content] => Introduction
When I designed DRAM chips at Intel I wanted to simulate at the worst case process corners to help make my design as robust as possible in order to improve yields. My manager knew what the worst case corners were based on years of prior experience, so that's what I used for my circuit simulations.
Today it's not so intuitive what the worst case process corners are for each specific IC design, so you could just use brute force Monte-Carlo simulations to find them. This approach takes a massive amount of time, CPUs and SPICE licenses. There has to be a better way.

Variation Analysis at DAC
My DAC schedule got completely filled this year on Sunday thru Wednesday, so I didn't get to hear from Solido about what's new. As soon as DAC ended and I blogged my trip reports I soon heard from Solido, so we scheduled some time in July to review what they presented at DAC in San Diego.

I spoke by phone with Kris Breen, Director of Corporate AEs and he walked me through their DAC presentation and demo.



Also on the call was Amit Gupta, CEO of Solido.


DAC Presentation Title - Variation Analysis and Design Software for Custom ICs.

The Solido mission is to analyze variation impact, identify electrical hotspots, then fix specification failures. They've been in business since 2005 and are growing, always a good sign to look for.

Amit's first EDA company was Analog Design Automation which grew for 5 years and was then sold to Synopsys, it was more of an optimization company.

Q: Who would benefit from using tools from Solido?
A: IC Designers that work on:

  • Analog (Transistor level)
  • IO
  • Memory
  • Std Cell

Q: At what process node did variation analysis become important?
A: We started seeing customers benefit from variation analysis at the 130nm node.

Q: Why is variation analysis important in the design process?
A: If you don't account for variation analysis then your design can have unacceptably low yield levels, or you may be over-designing or under-designing.

Q: What types of variation should an IC designer be concerned about?
A: We categorize seven types of variation:
[LIST=1]
  • Environmental (voltage, temperature)
  • Loading
  • Parasitic dependent effects
  • Layout dependent effects
  • Power dependent effects
  • Global process variation
  • Local process variation

    Q: What would be a first step with your tools?
    A: We recommend that you first identify electrical hotspots.

    Q: Once you find a hotspot do your tools change or optimize my transistor sizes automatically?
    A: No, we don't optimize your transistor sizes. You have to make that decision based on feedback from our tools, change sizes, then analyse the effects of your new design. We make the whole process easy.

    Q: How would your tools fit into the AMS Reference Flow from TSMC?
    A: Solido tools fit into the AMS Reference Flow 2.0 in five sub-flows:

    • Advanced PVT
    • Advanced Monte Carlo
    • Layout-Dependent Effects (not a product yet)
    • Parasitic Constraint Creation (not a product yet)
    • Power Integrity Constraint Creation (not a product yet)

    Solido Products and Partners
    Here's the overview picture of Solido products. You continue using your favorite circuit simulator (Spectre, APS, HSPICE, HSIM, AFS, FineSim, Eldo, internal SPICE) along with the foundry-supplied PDK (TSMC, GLOBALFOUNDRIES, Internal for IDMs).



    New at DAC 2011

    • Fast PVT (still Beta), finds the worst case corners about 5-50X faster than running all possible combinations. This is a huge time saver for circuit designers.



    • High-Sigma Monte Carlo, 100x to 1M x faster than pure MC (only uses about 1,000 runs)
    • DesignSense, an interactive, goal-oriented, variation-aware sensitivity tool.

    Q: Which SPICE circuit simulators does Variation Designer work with?
    A: Really any SPICE Simulator – your favorite SPICE, Analog FastSPICE, FastSPICE or internal simulator.

    Q: How do you speed up all of these circuit simulations?
    A. We can run them in parallel on multiple CPUs or cores (300 to 1000 in use now).

    Q: Do your tools run in the cloud as a service?
    A: The cloud looks interesting to us, stay tuned.


    Q: What is different with your Advanced PVT Verification?
    A: Our tool provides fast speed, SPICE accuracy and is scalable.


    The number of corners is rising dramatically with each new generation of process technology and this tool quickly finds the worst-cast PVT corners for your specific design.

    Q: Can you prove that this tool finds the worst-case corner every time?
    A: Not exactly, but it’s within a percent or so of the worst case PVT corner.


    Demo: Fast PVT (Beta)

    I saw an OpAmp example where:

    • 3,645 PVT corner combinations

      • Run Fast PVT corner extractions (quickest to find failures)
      • Fast PVT corner verification (more accurate to find worst case PVT corner)


    • More simulations than corner extractions, more accuracy too (20X speed up over exhaustive simulation)

      • -Looking at DC gain, phase margin, Unity Gain Bandwidth, Idc, Noise (compares prediction versus simulated)
      • Fast PVT corners



    Q: Can you create so much SPICE data that it fills up the hard disk?
    A: It’s smart enough to keep the results small in size, results can also be compressed.


    Demo: DesignSense (where to work on a design to fix failing corners)


    • Sensitivity Analysis, perturbation for all devices in design
    • Independent Sweeps (individual devices)
    • Combination Sweeps (groups of devices together)
    • Visualize the sensitivity of device values across your worst-case PVT corners (previously extracted or simulated)
    • Device combination parameters can be plotted versus spec

    Q: Is this an optimization tool?
    A: No, it tells you sensitivity in your design. You can use Variation Designer along with an Optimizer to get better designs
    sooner. Optimizers take much time to setup correctly and efficiently, it’s quicker to look at DesignSense results, make a judgement, tweak sizes.


    Q: Who are using these new tools?
    A: STARC has recently adopted Solido tools. They are using Variation Designer to find worst cases, and then improve design in as little as 7 hours.


    Q: How long would it take to optimize my OpAmp using DesignSense and PVT?
    A: You would get optimized results within a work day.

    Q: What’s the learning curve for Variation Designer?
    A: It's easy to get started out of the box within a day or two. Running Fast PVT has an easy learning curve. Running High-Sigma MC takes longer to learn. There are help buttons in context of every dialog that you use.

    Q: How often do you release your software?
    A: As needed, about 3-4 times per year for point releases. Minor releases as needed for hot fixes.


    Six-Sigma Analysis and Design: 6 sigma analysis at 3 sigma costs (time)

    • Capacity? About a 1,000 parameters is practical (5 parameters per device, 200 devices in design)
    • - MC: 1,000,000 samples run in 8 days, 0 failures to spec
    • - HSMC: 1,000,000 samples run (then focus on the tail), 531 samples simulated (10 minutes 15 seconds)
    • - HSMC (5 sigma): 100M samples (after 400 samples then focus on tail), automatically stops, 738 samples simulated (2 hour 14 minutes), 156 failures
    • - Memory Designers love using this tool (Qualcomm used this on a memory bit cell design, Synopsys AMS dinner at DAC – 100 HSPICE licenses)
    • - Now that you found the 156 failures in HSMC then run DesignSense to make the design pass all these conditions

    Advanced MC Analysis (MC+) – Fast (2x to 10x faster run times, can extract statistical corners at a target yield)

    Demo of MC+



    • Choose the number of samples desired, Tasks: Verify Design to 3 sigma target
    • Same OpAmp design used (folded gain, boosting Op Amp, about 100 to 150 devices)
    • Visualize the design results
    • After 23 samples it shows that target yield of 3 sigma cannot be reached (How do you fix this?)
    • Statistical Corner Extraction run. Found 3 sigma corners in only 87 more simulations.
    • Graphical display of sensitivity of all devices and impact on specs

    Summary
    Transistor-level IC designers responsible for analog, IO, memory and standard cells should check out the methodology offered by Solido to find which process corners affect their designs the most, then tweak their designs to be more robust. You continue to use familiar SPICE or Fast SPICE circuit simulators but in a new, more intelligent method than brute-force monte-carlo and get results in a fraction of the time.

    A product video demonstration is available HERE.



     [post_title] => Solido - Variation Analysis and Design Software for Custom ICs [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => solido-variation-analysis-and-design-software-for-custom-ics [to_ping] => [pinged] => [post_modified] => 2019-06-14 20:53:02 [post_modified_gmt] => 2019-06-15 01:53:02 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/solido-variation-analysis-and-design-software-for-custom-ics.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [6] => WP_Post Object ( [ID] => 705 [post_author] => 28 [post_date] => 2011-08-15 15:00:00 [post_date_gmt] => 2011-08-15 15:00:00 [post_content] => First, I would like to congratulate Samsung on their first 20nm test chip press release. Some will say it is a foundry rookie mistake since real foundries do not discuss test chip information openly. I like it because it tells us that Samsung is 6-9 months BEHIND the number one foundry in the world on the 20nm (gate-last HKMG) process node. Samsung gave up on gate-first HKMG? ;-)

    Unfortunately, the latest news out of TSMC corporate is that 28nm revenues will be 1% of total revenues in 2011 versus the forecasted 2%. Xbit Labs did a nice article here. The official word is that:

    "The delay of the 28nm ramp up is not due to a quality issue, we have very good tape-outs. The delay of ramp up is mainly because of softening economy for our customers. So, customers delayed the tape-outs. The 28nm revenue contribution in the Q4 2011 will be roughly about 1% of total wafer revenue," said Lora Ho, senior vice president and chief financial officer or TSMC.

    TSMC's competitors on the other hand, are whispering that there is a 28nm yield problem, using the past 40nm yield ramping issues as a reference point. Rather than speculate and pull things out of my arse I asked people who actually have 28nm silicon how it is going. Unanimously it was, “TSMC 28nm yield is very good!” Altera and Xilinx are already shipping 28nm parts . The other markets I know with TSMC 28nm silicon are microprocessors, GPUs, and MCUs.

    "We are far better prepared for 28nm than we were for 40nm. Because we took it so much more seriously. We were successful on so many different nodes for so long that we all collectively, as an industry, forgot how hard it is. So, one of the things that we did this time around was to set up an entire organization that is dedicated to advanced nodes. We have had many, many tests chips run on 28nm, we have working silicon," said Jen-Hsun Huang, chief executive officer of Nvidia.

    It is easy to blame the economy for reduced forecasts after what we went through in 2009 and the current debt problems being over reported around the world. The recent US debt debacle is an embarrassment to every citizen of the United States who votes. Next election I will not vote for ANY politician currently in office, but I digress….

    So the question is: Why do you think TSMC is REALLY reporting lower 28nm revenues for 2011?

    Consider this: TSMC is the first source winner for the 28nm process node, without a doubt. All of the top fabless semiconductor companies will use TSMC for 28nm including Apple, AMD, Nvidia, Altera, Xilinx, Qualcom, Boradcom, TI, LSI, Marvell, Mediatek, etc……. These companies represent 80%+ of the SoC silicon shipped in a year (my guess).

    One of the lessons semiconductor executives learned at 40nm is that silicon shortages delay new product deliveries, which cause billions of dollars in lost stock valuation, which gets you fired. Bottom line is semiconductor executives will be much more cautious in launching 28nm products until there is excess capacity, which will be mid 2012 at the earliest.

    Other relevant 2011 semiconductor business data points:

    [LIST=1]
  • The Android tablet market is DOA (iPad2 rules!)
  • The PC market is dying (Smartphone and tablets, Duh)
  • Mobile phones are sitting on the shelf (Are we all waiting for the iPhone5?)
  • Anybody buying a new car this year? Not me.
  • Debt, debt, unemployment, debt, debt, debt…….

    Not all bad news though, last Friday was the 30[SUP]th[/SUP] anniversary of the day I met my wife and here is how great of a husband I am: First I went with my wife to her morning exercise class. 30+ women and myself dancing and shaking whatever we got. It was a very humbling experience, believe me! Next was a picnic on Mt Diablo recreating one of our first dates, then dinner and an open air concert at Blackhawk Plaza. Life as it should be!





     [post_title] => TSMC 28nm and 20nm Update! [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => tsmc-28nm-and-20nm-update [to_ping] => [pinged] => [post_modified] => 2019-06-14 21:39:50 [post_modified_gmt] => 2019-06-15 02:39:50 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/tsmc-28nm-and-20nm-update.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [7] => WP_Post Object ( [ID] => 709 [post_author] => 9491 [post_date] => 2011-08-15 10:48:00 [post_date_gmt] => 2011-08-15 10:48:00 [post_content] =>  So Google is buying Motorola Mobility for $12.5B. If you are a partner of Google using Android then this has both upside and downside. The upside is that Motorola, having been in wireless for longer than almost anyone, presumably has a pretty good patent portfolio that can be used to defend against Apple, Nokia, Microsoft et al. The downside, of course, is that now Google has its own in-house handset company competing with you, and although right now they claim they will keep the playing field level, in the long run things don't always work out that way.

    For now the partners are putting positive spin on it. For instance, here is the CEO of Sony-Ericsson:“I welcome Google‘s commitment to defending Android and its partners.”


    Everyone else is equally positive. But it could turn nasty if Motorola (don't know if they are keeping the name) is either very successful (and therefore makes everyone else less successful) or unsuccessful (in which case Google will be tempted to give it an edge by getting a newer or better version of Android). [post_title] => Google buying Motorola [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => google-buying-motorola [to_ping] => [pinged] => [post_modified] => 2019-06-14 21:39:45 [post_modified_gmt] => 2019-06-15 02:39:45 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/google-buying-motorola.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [8] => WP_Post Object ( [ID] => 708 [post_author] => 4 [post_date] => 2011-08-15 10:42:00 [post_date_gmt] => 2011-08-15 10:42:00 [post_content] => If you did not have the chance to attend the famous Denali party at DAC 2011, you may want to go to Cadence VIP seminar to be held on Thursday, August 25, 2011, from 1:00 - 4:15pm at Cadence Headquarters: 2655 Seely Avenue, San Jose, Building 10. To register, click here. The atmosphere could be slightly different, as during Denali party the VIP from Cadence were the stars of the show, when for the seminar the stars will be the VIP for AMBA4 ACE, PCI Express gen-3, USB 3.0 and DDR4, to mention a few. In this seminar Cadence will propose case studies from experts in the field addressing the most challenging issues when it comes to verifying today's most important interfaces such as the four above listed.







    I have blogged about Cadence VIP, or VIP in general, in the past:



    Yalta in EDA: Cadence stronger in VIP territory…



    Interface IP: VIP wiki



    IP would be nothing without VIP…but what is the weight of VIP market?





    If you can make it (and you live in the Silicon Valley…), and you need to know more about VIP or need to be updated about the latest product, as Cadence is leading the VIP market and has built a wide port-folio, covering most of the existing Interfaces, you will certainly make a wise investment! To register to this VIP seminar, just go here.



    Or, if you cannot make it, have a look at Cadence impressive VIP port-folio (just click and see the product from Cadence web site):













    [post_title] => Cadence VIP Seminar: next stop after Denali party, August 25th in San Jose [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => cadence-vip-seminar-next-stop-after-denali-party-august-25th-in-san-jose [to_ping] => [pinged] => [post_modified] => 2011-08-15 10:42:00 [post_modified_gmt] => 2011-08-15 10:42:00 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/cadence-vip-seminar-next-stop-after-denali-party-august-25th-in-san-jose.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [9] => WP_Post Object ( [ID] => 703 [post_author] => 23928 [post_date] => 2011-08-15 07:00:00 [post_date_gmt] => 2011-08-15 07:00:00 [post_content] => Wyatt Earp probably wasn’t thinking of OPC when he said, “Fast is fine, but accuracy is everything,” but I’ll adopt that motto for this discussion of full-chip OPC and post-OPC verification models.

    Accuracy
    is the difference between the calibrated model prediction and the calibration wafer result. Accuracy depends on several factors, principally the intrinsic ability to represent the patterning trends through target size, pitch, and pattern shape for 1D and 2D structures at a given process condition. Calibration test pattern design coverage is important whenever model accuracy is in question.

    Additionally, because you judge OPC model prediction against experimental data, you must consider the experimental errors associated with the metrology data. For an ensemble of different test patterns, a model’s accuracy is limited by the experimental noise “floor.” Multiple repeat measurements (across wafer, across field) provide a better statistical representation and lower this noise contribution to the model. It is interesting to note that the standard error in the determination of the mean for typical OPC calibration structures is 0.5 nm for 1D and 1.5 nm for 2D.

    The degrees of freedom in the model will interact with the metrology noise such that it is possible to “over fit” the physical phenomena and start fitting the experimental noise.How can you quantitatively express the accuracy of a model? Metrics include maximum error, error range, chi-squared goodness of fit, and others. But one of the most useful is the “root mean square error value,” or errRMS (Equation 1) associated with the test pattern ensemble. This weighting (w) allows users to assign more importance to certain known critical design pitches. CDs may be used instead of EPE as well.

     [INDENT=2]Equation 1. CDsim[SUB]i[/SUB] is the model mean for each point i (measurement location); CDmeas[SUB]i[/SUB] is the data mean for each point i ; w is the user-specified weighting for each point i


    An interesting variant of RMS error (see Schunn and Wallach 2005), which accounts for sample metrology error directly, is the scaled RMS deviation (Equation 2). This objective function more heavily penalizes errors associated with precisely known data points than for data points with CDs having larger uncertainties.

     [INDENT=2]Equation 2. s[SUB]i[/SUB] is the standard deviation for each data mean i; n[SUB]i[/SUB] is the number of data values contributing to each measured mean; k is the number points i


    A related, but ultimately more important characteristic is model predictability. The duty of the OPC or post-OPC verification model is to correctly predict the patterning for every possible layout configuration that can appear per the design rules in the full chip. The number of unique design constructs for low k[SUB]1[/SUB] lithography is tremendous; several orders of magnitude more than could ever be reasonably used to train the model. If you divide a master set of patterns into two sets--use one half to train the model, and the other half to verify--the errRMS fitness should be as low on both sets.

    Another method involves including the complex 2D structures of the verification patterns, and then comparing the simulated contour with the experimental contour. If verification fitness is significantly worse than calibration fitness, the model is not sufficiently predictive. In addition, the model must account for CD variability arising from manufacturing process variability. Principle among these are focus, exposure, and mask CD variations (Figure 1).

    [INDENT=2] Figure 1. Example plot of model error RMS for various focus and exposure conditions. Model was calibrated at dose = Nom and focus = 0. Model fitness was then characterized for various defocus and exposure conditions.

    As will be outlined in a future installment of this series, the ability of a model to faithfully predict various pattern failure modes is also important. These failures typically manifest more severely as these manufacturing process parameters vary. A final consideration related to predictability is model portability. Of course, if an entirely new photoresist material, PEB temperature, or etch recipe is implemented for manufacturing, you will need a new model calibration. But if some aspect of the exposure step is slightly altered, such as NA or illumination source intensity / polarization, you should be able to “port” the same resist model and change only specific optical parameters. This is particularly helpful in early process development, when an existing process model is used to simulate next node printing with whatever new RET capabilities may become available. The degree to which the model can decouple optical exposure from resist processing is related not only to the details of the resist model, but also to the nature of the approximations “upstream” in representing the mask and optical system. The details of these mask and optical models will be the topic of my next installment in this series of articles. Stay tuned.

    --John Sturtevant, Mentor Graphics

    P.S. In case you missed them, go readPart 1 and Part 2 of this series. Then continue with Part 4.

    [post_title] => OPC Model Accuracy and Predictability – Evolution of Lithography Process Models, Part III [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => opc-model-accuracy-and-predictability-evolution-of-lithography-process-models-part-iii [to_ping] => [pinged] => [post_modified] => 2019-06-14 20:52:59 [post_modified_gmt] => 2019-06-15 01:52:59 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/opc-model-accuracy-and-predictability-evolution-of-lithography-process-models-part-iii.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) ) [post_count] => 10 [current_post] => -1 [in_the_loop] => [post] => WP_Post Object ( [ID] => 716 [post_author] => 9491 [post_date] => 2011-08-17 19:18:00 [post_date_gmt] => 2011-08-17 19:18:00 [post_content] =>  When you think of Indian music you might think of ragas for the sitar. But when you think of Indian MUSIC, that is the Magma user group meeting (Magma Users Summit for Integrated Circuits) coming up on September 7th in Bangalore (note: the date has changed from when it was originally announced). It is at Vivanta by Taj on M G Road.

    There is a guest keynote by Balajee Sowrirajan of Texas Instruments OMAP business unit on Trends and challenges in designinbg wireless application processor--what is the need of the day? at 9.30am.

    The second keynotet is at 12.35pm, just before lunch, by Rajeev Madhavan, Magma's CEO.

    There are other presentations by TI, Qualcomm, ARM, Netlogic, Microchip and Silicon One.

    More information, including the complete agenda, is here.

    To register, go here.

    [post_title] => MUSIC in Bangalore [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => music-in-bangalore [to_ping] => [pinged] => [post_modified] => 2019-06-14 21:39:53 [post_modified_gmt] => 2019-06-15 02:39:53 [post_content_filtered] => [post_parent] => 0 [guid] => https://35.226.139.164/uncategorized/716-music-in-bangalore/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [comment_count] => 0 [current_comment] => -1 [found_posts] => 6856 [max_num_pages] => 686 [max_num_comment_pages] => 0 [is_single] => [is_preview] => [is_page] => [is_archive] => [is_date] => [is_year] => [is_month] => [is_day] => [is_time] => [is_author] => [is_category] => [is_tag] => [is_tax] => [is_search] => [is_feed] => [is_comment_feed] => [is_trackback] => [is_home] => 1 [is_privacy_policy] => [is_404] => [is_embed] => [is_paged] => 1 [is_admin] => [is_attachment] => [is_singular] => [is_robots] => [is_posts_page] => [is_post_type_archive] => [query_vars_hash:WP_Query:private] => 2f3358c565b8b2ece286edb68c39236f [query_vars_changed:WP_Query:private] => [thumbnails_cached] => [stopwords:WP_Query:private] => [compat_fields:WP_Query:private] => Array ( [0] => query_vars_hash [1] => query_vars_changed ) [compat_methods:WP_Query:private] => Array ( [0] => init_query_flags [1] => parse_tax_query ) [tribe_is_event] => [tribe_is_multi_posttype] => [tribe_is_event_category] => [tribe_is_event_venue] => [tribe_is_event_organizer] => [tribe_is_event_query] => [tribe_is_past] => )
  • MUSIC in Bangalore

    MUSIC in Bangalore
    by Paul McLellan on 08-17-2011 at 7:18 pm

    When you think of Indian music you might think of ragas for the sitar. But when you think of Indian MUSIC, that is the Magma user group meeting (Magma Users Summit for Integrated Circuits) coming up on September 7th in Bangalore (note: the date has changed from when it was originally announced). It is at Vivanta by Taj on M G Road.

    There… Read More


    Fast Track your SoC Design

    Fast Track your SoC Design
    by Paul McLellan on 08-17-2011 at 5:24 pm

    Atrenta has four seminars coming up on SoC realization. More and more design is actually about finding IP and integrating it together at the block level, and then handing it off to a standard RTL to GDSII flow. The three focus areas are:

    • finding quality IP faster
    • accelerating IP integration and SoC assembly
    • handing off RTL successfully.
    Read More

    ANSYS Regional Conference

    ANSYS Regional Conference
    by Paul McLellan on 08-17-2011 at 3:15 pm

    Next Tuesday, August 23rd, is the ANSYS Regional Conference for Silicon Valley. It takes place at the Techmart Network Meeting Center. Apache has three presentations during the day:

    • 9.25-9.45 Andrew Yang Introducing Apache Design Solutions
    • 11.00-11.30 Methodology for delivering power-efficient designs from concept to
    Read More

    Mr. TTL’s Future is Analog: Time to Sell OMAP to Broadcom

    Mr. TTL’s Future is Analog: Time to Sell OMAP to Broadcom
    by Ed McKernan on 08-17-2011 at 1:00 am

    Mr. TTL (otherwise known as Texas Instruments or TI) has had a great run in the cellular market but it is time to decamp. The future is Analog and OMAP must depart to one of the remaining players looking to win the Smartphone and Tablet market. TI is exiting the market so it can focus on the high volume analog market.

    On first sight, the … Read More


    Captain Ahab Calls Out for the Merger of nVidia and AMD

    Captain Ahab Calls Out for the Merger of nVidia and AMD
    by Ed McKernan on 08-16-2011 at 8:00 pm

    Call me Ishmael. Some years ago –in the mid 1990s – having little or no money in my purse and nothing particular to interest me on shore, I thought I would sail the startup ship Cyrix and see the watery part of the PC world. Whenever I find myself grim about the mouth or pause before coffin warehouses, and bring up the rear of every funeral… Read More


    Solido – Variation Analysis and Design Software for Custom ICs

    Solido – Variation Analysis and Design Software for Custom ICs
    by Daniel Payne on 08-15-2011 at 7:11 pm

    Introduction
    When I designed DRAM chips at Intel I wanted to simulate at the worst case process corners to help make my design as robust as possible in order to improve yields. My manager knew what the worst case corners were based on years of prior experience, so that’s what I used for my circuit simulations.… Read More


    TSMC 28nm and 20nm Update!

    TSMC 28nm and 20nm Update!
    by Daniel Nenni on 08-15-2011 at 3:00 pm

    First, I would like to congratulate Samsung on their first 20nm test chip press release. Some will say it is a foundry rookie mistake since real foundries do not discuss test chip information openly. I like it because it tells us that Samsung is 6-9 months BEHIND the number one foundry in the world on the 20nm (gate-last HKMG) process… Read More


    Google buying Motorola

    Google buying Motorola
    by Paul McLellan on 08-15-2011 at 10:48 am

    So Google is buying Motorola Mobility for $12.5B. If you are a partner of Google using Android then this has both upside and downside. The upside is that Motorola, having been in wireless for longer than almost anyone, presumably has a pretty good patent portfolio that can be used to defend against Apple, Nokia, Microsoft et al. The… Read More


    Cadence VIP Seminar: next stop after Denali party, August 25th in San Jose

    Cadence VIP Seminar: next stop after Denali party, August 25th in San Jose
    by Eric Esteve on 08-15-2011 at 10:42 am

    attachment

    If you did not have the chance to attend the famous Denali party at DAC 2011, you may want to go to Cadence VIP seminar to be held on Thursday, August 25, 2011, from 1:00 – 4:15pm at Cadence Headquarters: 2655 Seely Avenue, San Jose, Building 10. To register, click here. The atmosphere could be slightly different, as during DenaliRead More


    OPC Model Accuracy and Predictability – Evolution of Lithography Process Models, Part III

    OPC Model Accuracy and Predictability – Evolution of Lithography Process Models, Part III
    by Beth Martin on 08-15-2011 at 7:00 am

    Wyatt Earp probably wasn’t thinking of OPC when he said, “Fast is fine, but accuracy is everything,” but I’ll adopt that motto for this discussion of full-chip OPC and post-OPC verification models.

    Accuracy
    is the difference between the calibrated model prediction and the calibration wafer result. Accuracy depends on several… Read More