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Imec’s An Steegen Talks Future Process Technology

Imec’s An Steegen Talks Future Process Technology
by Paul McLellan on 06-27-2015 at 7:00 am

 I’m an An Steegen groupie. Once or twice a year I see a presentation by her and it is a great summary in a ridiculously short period of time of all the potential upcoming semiconductor technologies. Yesterday was my annual fix at the imec Technology Forum (ITF). Today I got to sit down with her at the conference center.

An is different from most people at imec who, as a friend of mine described it, “are born at imec, do their PhD at imec and die there.” An went to the US and worked for IBM for over a decade in Fishkill, NY. She is now the SVP of process technology for imec. She is obviously not the only process technologist who know all this stuff. For sure every semiconductor company has their own experts. But she is the most free to talk about it. When did you last see TSMC or Intel giving details of all the work they are doing beyond 5nm?

Imec works with all the leading edge semiconductor IDMs and foundries including Intel, TSMC, GF, Samsung, SK Hynix, Micron, Toshiba, Sandisk. There are over 300 engineers assigned from these companies to work at imec. They all work together on programs. Imec is a sort of neutral ground, but it also allows for pre-competitive R&D cost-sharing and gives everyone access to their pilot line for novel technologies and equipment (which they may not even have access to in their own companies).

 An sees part of their job as to see what technologies should be in the funnel for the future, then downselect it. Ultimately the semiconductor ecosystem has to make some decisions on what they will and will not do. The whole ecosystem needs to move since there is no good depending on a piece of equipment if nobody manufactures it, or on a material that is not available. For example, almost everyone decided on FinFETs after 20nm (or at it for Intel). Everyone has agreed not to worry about 450mm for the foreseeable future.

So I asked An what she saw as the most likely roadmap for the future.


First, push the fin as far as possible, higher and thinner fins. One big challenge, apart from the obvious fact that the higher and thinner the fin the more fragile it is, is to manage resistance and capacitance with very tall fins. Control of the process is also a big issue since everything is just a few atoms thick.

Next gate-all-round with lateral (parallel to the substrate) nanowires. Can relax the width a little versus fins.

Then stacking nanowires. The experience of vertical NAND flash and the techniques developed for doing that should help here too.

Next perhaps is vertical FETs. Unknown quite what the performance is. One nice feature of vertical FETs is that the gate-length can be varied just like in the olden days, by depositing thicker or thinner material. One big issue is how to connect to the bottom terminal of the gate.


Metrology is becoming a really big issue. All these vertical approaches also need the deposition to be conformal. There is also the possibility of local deposition which has new metrical needs.

The big challenge for the ecosystem is that we are still on a 2-year cycle but the roadmaps have to start really early so that everyone (equipment, manufacturers, materials, EDA, IP…) know what to get ready. This is especially acute with metrology who need to know where to focus.

EDA is no longer at arm’s length (nor is ARM, hoho) from the process stuff. Long gone are the days where SPICE parameters and design rules were all that were needed and the whole flow was up and running. Imec has something they call Design Technology Co-Optimization (DTCO) that focuses on this. For example, they worked closely with the EDA companies very early on double patterning which required huge changes to support all the coloring in everything from layout, place & route, verification, extraction and more.

A good example of what is required to move the ecosystem is spin devices. These are very very low power but slow. But so is a lot of IoT so maybe they are the perfect match. They are constructed in the backend in the metal stack. For sure active devices in the metal stack will break lots of EDA tools. I doubt you can even describe them in a PDK. But something like this clearly needs time to get ready. They can use the imec pilot line to fabricate the structures before, eventually, moving off to finalize details at each foundry.


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