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WP_Query Object
(
    [query] => Array
        (
            [paged] => 658
        )

    [query_vars] => Array
        (
            [paged] => 658
            [error] => 
            [m] => 
            [p] => 0
            [post_parent] => 
            [subpost] => 
            [subpost_id] => 
            [attachment] => 
            [attachment_id] => 0
            [name] => 
            [pagename] => 
            [page_id] => 0
            [second] => 
            [minute] => 
            [hour] => 
            [day] => 0
            [monthnum] => 0
            [year] => 0
            [w] => 0
            [category_name] => 
            [tag] => 
            [cat] => 
            [tag_id] => 
            [author] => 
            [author_name] => 
            [feed] => 
            [tb] => 
            [meta_key] => 
            [meta_value] => 
            [preview] => 
            [s] => 
            [sentence] => 
            [title] => 
            [fields] => 
            [menu_order] => 
            [embed] => 
            [category__in] => Array
                (
                )

            [category__not_in] => Array
                (
                )

            [category__and] => Array
                (
                )

            [post__in] => Array
                (
                )

            [post__not_in] => Array
                (
                )

            [post_name__in] => Array
                (
                )

            [tag__in] => Array
                (
                )

            [tag__not_in] => Array
                (
                )

            [tag__and] => Array
                (
                )

            [tag_slug__in] => Array
                (
                )

            [tag_slug__and] => Array
                (
                )

            [post_parent__in] => Array
                (
                )

            [post_parent__not_in] => Array
                (
                )

            [author__in] => Array
                (
                )

            [author__not_in] => Array
                (
                )

            [ignore_sticky_posts] => 
            [suppress_filters] => 
            [cache_results] => 
            [update_post_term_cache] => 1
            [lazy_load_term_meta] => 1
            [update_post_meta_cache] => 1
            [post_type] => 
            [posts_per_page] => 10
            [nopaging] => 
            [comments_per_page] => 50
            [no_found_rows] => 
            [order] => DESC
        )

    [tax_query] => WP_Tax_Query Object
        (
            [queries] => Array
                (
                )

            [relation] => AND
            [table_aliases:protected] => Array
                (
                )

            [queried_terms] => Array
                (
                )

            [primary_table] => wp5_posts
            [primary_id_column] => ID
        )

    [meta_query] => WP_Meta_Query Object
        (
            [queries] => Array
                (
                )

            [relation] => 
            [meta_table] => 
            [meta_id_column] => 
            [primary_table] => 
            [primary_id_column] => 
            [table_aliases:protected] => Array
                (
                )

            [clauses:protected] => Array
                (
                )

            [has_or_relation:protected] => 
        )

    [date_query] => 
    [queried_object] => 
    [queried_object_id] => 
    [request] => SELECT SQL_CALC_FOUND_ROWS  wp5_posts.ID FROM wp5_posts  WHERE 1=1  AND wp5_posts.post_type = 'post' AND (wp5_posts.post_status = 'publish' OR wp5_posts.post_status = 'expired' OR wp5_posts.post_status = 'tribe-ea-success' OR wp5_posts.post_status = 'tribe-ea-failed' OR wp5_posts.post_status = 'tribe-ea-schedule' OR wp5_posts.post_status = 'tribe-ea-pending' OR wp5_posts.post_status = 'tribe-ea-draft')  ORDER BY wp5_posts.post_date DESC LIMIT 6570, 10
    [posts] => Array
        (
            [0] => WP_Post Object
                (
                    [ID] => 695
                    [post_author] => 4
                    [post_date] => 2011-08-10 10:32:00
                    [post_date_gmt] => 2011-08-10 10:32:00
                    [post_content] => If Cadence is making money with large VIP port-folio, Synopsys has successfully deployed an acquisition strategy to build a large Design IP port-folio. Looking at these acquisitions will help understanding Synopsys positioning in the IP market. When they have started this acquisition campaign, back in 2002, their market share was a few % of a market weighting less than $1 Billion…




The first acquisition was InSilicon in July 2002. Synopsys bought IP for interface standards such as USB, PCI, Ethernet, and 1394. This was their first step in the Interface, standard based, IP market and they keep playing in this segment, doing pretty well as they are now the undisputed leader as we will see further in this blog.

Then they have acquired Cascade in October 2004. Cascade, was one of the very first companies involved in the new (at that time) PCI Express protocol. They plaid the game pretty well, their Controller IP being selected by the PCI-SIG as the reference system to be used for testing any new PCI Express system (IP, ASSP or board) during “plugfest”, in order to get the certification. Thus, CASCADE was were very well positioned to enjoy the first sales of PCIe IP, when you can charge for the license a price which is X3 or X4 that it will be a couple of years later! Even if Synopsys had already a design team developing a PCIe Controller (and PHY) IP, acquisition was a quick and efficient way to kill a dangerous competitor, and to jump start in this market with the positive image of an Innovator. At that time the PCI Express IP market, as reported by Gartner, was pretty small. Amazing to notice, three out the four companies ranked in the top 4, Rambus, ARM and Cadence have exited the market in the meantime (2007-2008). Rambus and ARM because it was not on line with their new business model. But Cadence came back in 2010 when they bought Denali, it’s too early to know what will be their success.



In 2007, Synopsys was enjoying business growth –and good market share- in almost every segment of Interface IP: USB, PCIe, SATA, except Memory Controller (DDRn). This market segment was strongly dominated by Rambus and Denali, which make sense as both companies where involved for long time in development around DRAM. As the ASIC market was moving to a SoC market (ASIC + embedded core), the need to integrate a Memory Controller to interface with external DRAM, in a more and more complex manner, was pushing the DDRn Controller IP sales. Once again, Synopsys decided for the faster and easier (providing you have deep pocket) way: they bought Mosaid in July 2007 and get access to the DDRn Controller IP market, which was not so big at that time:





In 2009 they were doing well in every segment of the Interface IP market, so the acquisition of the mixed-signal IP division of MIPS (in fact Chipidea bought in August 2007 for $147 million in cash!) in May 2009 for a mere $22 million was an opportunistic move. First, it brings a large port-folio of mixed signal IP (ADC, DAC and many more), allowing Synopsys to expand the penetration in the IP market, in a segment they have ignored so far. It was also a way to definitely kill any competition in the USB IP market, where they enjoyed already more than 60% market share and ChipIdea/MIPS 26%...




Also to notice, the fact that Chipidea was involved in two recent if not emerging protocols: HDMI and MIPI, even if this was not the reason for buying. This acquisition was just the kind of opportunity you can’t miss, and the reason why MIPS accept such a discounted price had to do with the recession, but also with the fact they didn’t succeed in running a mixed signal IP product line, where every design-in is almost a redesign, completely at the opposite with processor core.

So you could think that it was enough acquisitions. But the next important move on the chessboard came from cadence: they acquired Denali for $315M in May 2010! I am sure (even if I share no secret as I don’t really know it by fact) that Synopsys has to do with this pretty high price (a x7 multiple of Denali revenue), and that they have pushed up the bidding. Nevertheless, Denali was doing very well with DDRn Controller IP, and many analysts propose predictions above $100M for this IP segment. If you look for a way to expand your business by going in a place where you are not (Memory compilers and Libraries), and consolidate your share in DDRn Controller IP, then Virage Logic looks to be the right acquisition to do, and a smart way to answer to Cadence acquisition of Denali, is’n it? That was the last acquisition made by Synopsys, in June 2010. When you look at the DDRn Controller IP market figures for 2009, and when you know that the target was $10M for Virage Logic for 2010, you better understand it, even if adding a $40M to $50M yearly revenue coming from Memory Compilers and Libraries was also part of the equation, but the expected growth for these segments is almost null:




So, acquisition after acquisition, Synopsys has built a wide port-folio including:


and they have a dominant position in each product line. They have also acquired ARCprocessor core product line (through Virage Logic), and they clearly have a weak position here. Moreover, does Synopsys really want to compete with ARM core’s business? I am not sure, but we will see what will happen in the future…

Eric Estevefrom IPnest(a lot more about Interface IP here)






[post_title] => Yalta in EDA: but Synopsys ultra dominant in Interface IP territory… [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => yalta-in-eda-but-synopsys-ultra-dominant-in-interface-ip-territory [to_ping] => [pinged] => [post_modified] => 2019-06-14 20:52:53 [post_modified_gmt] => 2019-06-15 01:52:53 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/yalta-in-eda-but-synopsys-ultra-dominant-in-interface-ip-territory.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [1] => WP_Post Object ( [ID] => 693 [post_author] => 9491 [post_date] => 2011-08-09 17:42:00 [post_date_gmt] => 2011-08-09 17:42:00 [post_content] => It is no secret that SoC designs continue to increase in complexity and time-to-market windows are shrinking. While there is room for debate on just how big a fraction of SoC design effort goes on verification, there is no debating that it is a large part of the total.  Simulation is increasingly too slow, especially when software has to be verified against the hardware. In some areas, formal techniques can be attractive but they are not universally applicable. One attractive approach is to use FPGAs to build a prototype of all or part of the SoC use this for verification. However, one big challenge is that synthesis, place and route for an SoC-sized FPGA can take as long as a day. It is impossible to observe every signal in a large SoC and so the SoC must be re-synthesized each time that a change is required in which signals need to be kept track of. Full re-creation of all the layout each time a change is made in the choice of signals is too slow. ProtoLink Probe Visualizer is a new approach to the problem. By understanding the placement and routing within the FPGA it is possible to make changes incrementally and almost instantaneously. With the addition of an interface containing probe memory, the data that it is possible to collect goes from 10s of signals for limited cycles, with a one day turnaround on changes to the signal list, to thousands of signals for millions of cycles, with a few minutes to update the list. The whitepaper is here. [post_title] => Speeding Verification of FPGA Prototype Boards [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => speeding-verification-of-fpga-prototype-boards [to_ping] => [pinged] => [post_modified] => 2019-06-14 21:39:40 [post_modified_gmt] => 2019-06-15 02:39:40 [post_content_filtered] => [post_parent] => 0 [guid] => https://35.226.139.164/uncategorized/693-speeding-verification-of-fpga-prototype-boards/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [2] => WP_Post Object ( [ID] => 691 [post_author] => 9491 [post_date] => 2011-08-09 17:08:00 [post_date_gmt] => 2011-08-09 17:08:00 [post_content] => At DAC SpringSoft had a couple of video games set up, one about functional verification and one about, surprise, physical layout. But you didn't need to go to DAC, you can play them now:

Close in on Closure

Liberate your Layout



  [post_title] => Fun Break [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => fun-break [to_ping] => [pinged] => [post_modified] => 2019-06-14 21:39:39 [post_modified_gmt] => 2019-06-15 02:39:39 [post_content_filtered] => [post_parent] => 0 [guid] => https://35.226.139.164/uncategorized/691-fun-break/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [3] => WP_Post Object ( [ID] => 690 [post_author] => 4 [post_date] => 2011-08-08 08:50:00 [post_date_gmt] => 2011-08-08 08:50:00 [post_content] => …or a global recession, but that’s not the purpose of this blog. As everybody knows, Apple is designing and selling smartphones, only. Does it mean that only smartphones are generating profit in the mobile industry? As we have seen recently in Semiwiki, Apple makes 2/3 of profit of entire mobile industry.



Let’s have a look (below) at the complete picture of Phone revenue (yellow), profit (red), smartphone market share (green) and phone share (blue) for:

  • RIM, Apple, HTC
  • LG, Samsung
  • Sony-Ericsson, Nokia, Motorola

The first remark is that profit curve is almost duplicating the smartphone share curve. Moreover, when the company does not market smartphones (LG or Sony-Ericsson or Motorola) the profit curve is flat… equal to zero! Nokia is an exception, as they used to have the largest smartphone market share, now declining, and their profit are impacted by the company overall strategy in the mobile phone industry (where they still have the largest share).




Click on the picture to see it larger, if you still can't see enough, go here

This simply means that the current profit, and the future success for the handset manufacturers is intimately linked to their implication in the smartphone, just like if the largest part (75% of the shipments), feature phones and entry phone, did not count at all… at least in term of profit.

I have spent some time to survey MIPItechnology, and so far MIPI has been only used in the smartphone, so I had to look carefully at this handset segment. When I started the survey back in September 2010, the available figures for 2009 was 173 million smartphone. At the beginning of 2011, we had access to the 2010 figure: 304 million units! 75% year to year growth on such a market, where you count by hundred millions, it is something we never saw before in the electronic industry… That push me to build the forecast for the next five years, I share with you today:



Interesting, but what is the impact on our industry, SC (and EDA, Foundry and IP)?
Like the PC can be determined by the processor it integrates, smartphone can be characterized by the Application Processor it uses. If you have a look at OMAP5, you can see that it integrates two processor cores (Cortex M4 from ARM), plus a graphic processor core (SGX544 from Imagination technologies), an audio processor, a DSP core, tons of Interface IP (USB2, USB 3.0, MIPI CSI, DSI, DigRF and LLI, SATA, LPDDRn and many more) as well as IP functions for memories, internal interconnect and many more. Such a SoC is also a challenge for EDA tools (you have to deal with a lot of clock domains and be able to manage the power down states for all the functions), has to be processed on the latest technology nodes – from foundry or IDM – hopefully by dozen of million units when the SoC is successful. To summarize, Application processor is at the technology edge, both for EDA and manufacturing, requires building real partnership with IP vendors… and are sold at a small fraction of a CPU ASP: say $15 to $25. But more than 400 million will be sold this year, which is more than the overall number of CPU sold in PC segment.

As this market is served by a dozen of companies (Qualcomm Inc., Texas Instruments Inc., Samsung Electronics Co. Ltd., Marvell Technology Group Inc., and Nvidia Corp., ranked as the top five, respectively, of sellers of smartphone applications processors in the first quarter, according to a new report by Strategy Analytics and others, including the yet to be known Chinese start-up), the direct sales impact for IP and EDA should be –mathematically- higher than for the single two AMD and Intel. Especially if you take into account the time to market impact, forcing the companies involved into Application Processor design to outsource as many IP as it make sense. I am far to minimize their strengths when saying their design know how is first based on “IP integration” and “design for low power”. If it was so easy to do, Intel would now dominates this market too… which is not the case!

Another forecast is worth to look at, made by ABI research for the total Application processor market evolution up to 2016:



If in Q2 2011 Apple has made 2/3 of the profit for the entire mobile industry, shipping 20 million smartphones out of a market of slightly more than 100 million in Q2, we can say that most of the profit in the handset industry are coming from smartphone, even if they only represent 28% of the handset. This is only the beginning of the story, as the smartphone shipments has grown last year (2010) by 70%, for a 20% share of the handset market, and will continue to grow during the next five years with a 26% CAGR. This means that in 2016, we can expect just less than 900 million smartphone to reach the market, or, in other words, almost half handset will be smartphone at that date. This will generate a market for Application processor growing at the same rate, in units, and a bit less in value, due to the price erosion. There will be a direct impact on EDA and IP sales, as these SoC are ever more challenging and complex to design and the mobile industry demand in Time to Market impose to outsource ever and ever more IP.

Eric Esteve from IPnest
[post_title] => Smartphones shipments, Sky is the limit… [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => smartphones-shipments-sky-is-the-limit [to_ping] => [pinged] => [post_modified] => 2019-06-14 21:39:39 [post_modified_gmt] => 2019-06-15 02:39:39 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/smartphones-shipments-sky-is-the-limit.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [4] => WP_Post Object ( [ID] => 680 [post_author] => 28 [post_date] => 2011-08-07 16:00:00 [post_date_gmt] => 2011-08-07 16:00:00 [post_content] =>
Don’t get me wrong, I’m a big fan of AMD, I buy AMD based products whenever possible to prevent an innovation stifling Intel monopoly. Unfortunately Silicon Valley coffee house conversations continue to paint a bleak picture for AMD, even with a recent stock surge on better than expected revenue guidance for the rest of 2011. I’m sure Wall Street coffee house conversations do not track with ours and here’s why:

Intel has always been the semiconductor manufacturing technology leader but throughout the years AMD was very clever and kept pace. Unfortunately AMD went fabless last year and as a result will not be able to compete in the discrete microprocessor market (my opinion). AMD also has no mobile strategy so where will they be when tablets and phones replace laptops?

Today AMD is in production at 32nm SOI with the Ex AMD fab in Dresden which is very competitive with the current Intel 32nm HKMG process. Future AMD microprocessor generations however will use commercially available foundry processes which track a process node or two BEHIND Intel. You should also know that microprocessor manufacturing is unique and may not 100% adapt to a more generic foundry process.

Source: TechConnect

Mid next year AMD will have CPU/GPUs on 28nm HKMG processes but will they be price/performance competitive with the Intel 22nm Tri-Gate technology? The answer is probably NO, not in the discrete microprocessor market. Intel will also be the first to 450mm manufacturing which will bring a dramatic costs savings versus mainstream 300mm semiconductor manufacturing.

A glaring non-compete example is gross margins. How can AMD again achieve the 50%+ margin average required to compete profitably against Intel? AMD’s gross margins fell below 40% in 2008 and have yet to recover. As an example, take the most recent AMD Wafer Supply Agreement Amendment. A detailed analysis of this agreement is a blog in itself, especially with all of the redacted areas. Skip down to pages 8, 9, and 10 where the financial details are and tell me how AMD will even hit 40% gross margins in 2012. If you disagree let me know in the comment section and we can discuss in more detail.

To make a long blog short, AMD needs an exit strategy to be competitive with the Intel CPU dynasty. My first choice would be ATIC taking AMD private and integrating it with GlobalFoundries. Second choice would be for Samsung to buy AMD. Either way there would be a viable competitor to Intel. Or not, but it would certainly be fun to watch!

Don’t get me wrong, I’m not bashing ANYBODY here, I do this blog out of love. The SemiWiki mission statement is “For the greater good of the semiconductor design ecosystem”. I admire ATIC and what they have done for the semiconductor industry, I respect the accomplishments of AMD, and I’m the #1 fan of GlobalFoundries. But let's be honest, Intel is a force to be reckoned with and we had all be better prepared for the coming war of microprocessors!

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[post_title] => Samsung to Acquire AMD? [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => samsung-to-acquire-amd [to_ping] => [pinged] => [post_modified] => 2019-06-14 21:39:38 [post_modified_gmt] => 2019-06-15 02:39:38 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/samsung-to-acquire-amd.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [5] => WP_Post Object ( [ID] => 676 [post_author] => 9491 [post_date] => 2011-08-07 15:28:00 [post_date_gmt] => 2011-08-07 15:28:00 [post_content] =>  The last of the current series of webinars is on Sentinel-PSI,IC-Package, Power and Signal Integrity Solution. It will be at 11am Pacific time on Thursday 11th August. It will be conducted by Dr. Tao Su, product manager of the Sentinel products. Dr. Su has many years of experience in the EDA industry and is specialized in power integrity and signal integrity analysis for package and PCB. He received his Bechelor’s degree in Electrical Engineering from Tsinghua Univ., Beijing, China, and his MS and PhD degree from the University of Texas at Austin.

This is a 3D full-wave electromagnetic solver for power and signal integrity analysis of IC package and PCBs, with the ability to perform DC (static), AC (frequency domain), and transient (dynamic) simulations from a single environment. Based on the fast finite element method (FFEM), Sentinel-PSI provides the accuracy of a conventional full-wave tool, with the unparalleled capacity to handle an entire package or board design. Sentinel-PSI is seamlessly connected to other Apache products in system-level analysis, and is linked with Sentinel-SSO to perform system-level I/O-SSO simulations.

Register for the webinar here.



 [post_title] => Sentinel-PSI Webinar [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => sentinel-psi-webinar [to_ping] => [pinged] => [post_modified] => 2019-06-14 20:52:50 [post_modified_gmt] => 2019-06-15 01:52:50 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/sentinel-psi-webinar.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [6] => WP_Post Object ( [ID] => 679 [post_author] => 20367 [post_date] => 2011-08-07 13:11:00 [post_date_gmt] => 2011-08-07 13:11:00 [post_content] =>  Intel will not win the tablet market with any of the various Atom chips rolling out at 32nm, 22nm and even 14nm. They are too late to a game that Apple owns 90% of today and will so in the future. All of these ultra low power atom versions are like the Saturn test rocket developments that preceded the Apollo 11 Moon Landing. They are necessary test chips where engineers at Intel try out new circuit designs and architectural tradeoffs in tuning power vs performance in preparation for a set of chips co-architected with Apple and appearing in 14nm.

Many threads lead me to the above conclusion. But from a business perspective there are huge benefits to Apple and Intel joining hands. The 90% market share in the tablet market and the growth coming from the MAC Air notebooks are key indicators to the future of the mobile market. Both are kissing cousins in term of their form-factors and hardware features. The clear driver for the form-factors was economical Flash memory in substitution for HDDs and the elimination of DVD drives. The thickness shrunk and the weight dropped to the point you can hold them with one hand comfortably.

There are two main differences. First is the light iOS of the iPAD and the heavier MAC O/S of the MAC Air. And Second is the $25 ARM A5 processor in the iPAD vs. the $220 Intel i5 ULV in the MAC Air. A merging of OS interoperability and lower x86 CPU pricing is coming.

With a co-architected family of processors running in Intel’s fab – the costs of today’s $25 A5 could drop to as low as $15. The math is key here. Let’s say at the low end Apple ships 50MU pads in 2014 at a $10 savings using Intel (based on smaller die) = $50MU *$10 = $500M. Now factor in market share gains that Apple would accrue if they added a higher performance CPU based iPAD at similar battery life (something Intel can deliver). Apple stretches out their market TAM while retaining a high market share with Intel delivering the CPUs. But what would the high end of the CPU line look like for iPAD? Start looking at the MAC Air.

The low end line of the MAC Air sells for $999 and uses the $220 Sandy Bridge i5 ULV processor. This $ percentage of CPU to system price is very high historically for Intel and is one of the reasons the PC Clones are having difficulty undercutting Apple’s $999 price. Intel knows if they don’t offer a much lower cost CPU, then the iPAD cannibalizes the low end, light-weight notebook PC market.

To the plus side for Intel, the attractiveness of the MAC Air package and its ability to run all MAC O/S Apps makes it a competitive alternative to the iPAD. If customers had the choice of a MAC Air that sells for $200 or $300 less and an iPAD, then I believe a large majority would choose the MAC Air. This is my cursory read having played in this market a long time.

At the moment and for the next 12 months, Intel’s hands are tied. The MAC Air uses an Intel ULV processor that has a TDP of 17W. Intel can not yield enough at this power level that would allow them to sell a low end processor (an i3 ULV for $75). At $150 reduction, a system price would drop by $300 to $699.

With Ivy Bridge (using 22nm Tri Gate process), Intel will get an immediate drop in TDP by 50% at the same performance level and cores and caches. Look for Intel to yield near 100% at 17W TDP to enable a $75 CPU by mid 2012. Then look for them to introduce a lower power ULV at around 9-10W at the same yield and price points today. So does Apple go more aggressive MAC Air in mid 2012 with a 10W TDP while the PC clones are going with the 17W TDP. My guess is yes and it will allow them to claim more battery life and retain higher pricing (maybe $899 at the lowest). The key here is that Apple wants the iPAD to flourish and expand rapidly in the next 18 months so that it is effectively game over for tablet competitors. They than can decide to balance the iPAD vs MAC Air volume.

Intel will turn the crank one more time with the Haswell architecture in 2013 where the TDP will be lowered again and Intel will offer aggressive price points on x86 processors that demonstrate 3-7W TDP. Standby power will be extremely low and the advantages of ARM’s low power are eliminated. Then it is a game of who can build what the cheapest.

There have several speculative articles lately on Apple using a future multi-core A6 in MAC Air to lower the cost and to set their own destiny. Furthermore by 2016 they would get to a 64 bit quad core and replace x86 in MAC Book Pro and the desktop. I think these rumors are spread for a reason. Apple wants to see better pricing out of Intel so that they can gain market share in the MAC Air and MAC Book Pro. Apple can not execute completely on their vision of winning the corporate market with products that use just Intel’s mid range and high end processors. In other words they are not using anything less than $200 on Intel’s price list.

As Apple scans out over the horizon then, they see that their dominance in Tablet and iPhone can come to fruition in the PC space if they get a few things that are unique to them and not available to others. This is where, if they play the Intel relationship right they can drive their 5% worldwide market share into high double digits. This may sound over the top … but there are changes on the way to MAC Pro as well that complete Apple’s frontal attack.

Part of Apple’s brand is based on things that they develop and in some cases based on a co-marketing development. The A4, A5 and A6 are seen as their gift to the mobile world in terms of performance at the right power. The Thunderbolt I/O developed with Intel and released before the rest of the world had access to it is a good example of technology co-marketing.

For Apple to retain its brand leadership, it needs to co-architect and be first to market with a new multicore processor that combines Intel x86 and process technology with a future A6 that includes Apple’s specified graphics. The multi-core solution will run both iOS and MAC OS. These processors will be built in 14nm and out the door late 2013 or 1H 2014. Intel will build a family of A6/x86 combo processors to allow low to moderately priced CPUs. Apple will have sole rights to the chips and can hide from its competitors the true cost of the CPUs. Apple MAC based PC will drop in price. On Intel’s side, they can continue to serve legacy x86 markets without a price conflict.

Finally Intel will use the Apple partnership to leverage other large volume customers to consider a partnership with x86 based CPUs that include customer proprietary IP and functions. But again Apple has the lead on others. This will be a win for Apple in terms of performance, cost and technology leadership. This will also be a win for Intel as it increases its overall market share in selling high $$$ sand.



 [post_title] => Apple Roadmaps Intel to 14nm [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => apple-roadmaps-intel-to-14nm [to_ping] => [pinged] => [post_modified] => 2019-06-14 21:39:36 [post_modified_gmt] => 2019-06-15 02:39:36 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/apple-roadmaps-intel-to-14nm.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [7] => WP_Post Object ( [ID] => 687 [post_author] => 4 [post_date] => 2011-08-07 05:42:00 [post_date_gmt] => 2011-08-07 05:42:00 [post_content] => …when Synopsys is getting the lion’s share in Interface IP. In Q2 2010, there was two major acquisitions in EDA world: Synopsys has bought Virage Logic (for more than $300M) when Cadence bought Denali for an equivalent amount. Synopsys bought a 100% IP focused company, when Cadence bought a strongly VIP focused company. Does it sound like Yalta in EDA world? Let’s have a look today at Cadence positioning in the VIP market, and keep for another blog Synopsys positioning in the IP territory.







Cadence preference for the VIP market is not dated from 2010. Back in 2008, Cadence made the acquisition of verification IP (VIP) assets from Yogitech SpA, IntelliProp Inc., and HDL Design House. to expands its existing VIP portfolio by five times to include over 30 standard protocols for wireless, networking, storage, multimedia, automotive, and more. With Denali acquisition, Cadence has even more heavily invested into VIP market as they bought a strong VIP port folio and competencies, mostly based on Memory (the “memory models” for standard products and DDRn VIP), and also PCIe and USB. Some leading edge IP were also in the basket, with PCIe 3.0 and even more important, DDRn memory controller, a segment where Denali has always had a good share, allowing Cadence to put a stone in Synopsys garden.



When you consider that Synopsys integrates their VIP into Design Ware, which means they do not try to value each VIP, you may think that Cadence should extract most of the value from the VIP segment, as they market one (functional verification) product by protocol standard. The list of supported protocol has been recently updated, and demonstrates the strong commitment of Cadence to this market:

· AMBA 4

· AMBA AHB

· AMBA AXI

· AMBA APB

· CAN

· Ethernet

· HDMI

· I2C

· JTAG

· LIN

· MIPI CSI-2

· MIPI DSI

· MIPI M-PHY

· MIPI SLIMbus

· MIPI UniPro

· MIPI DigRF v4

· OCP

· PCI Express

· PCI

· PLB

· SAS

· Serial ATA (SATA)

· Serial Rapid IO

· USB (with OTG)

· USB SuperSpeed
· DDR2

· DDR3

· DDR4

· DDR4 SDRAM

· DDR NVM

· EEPROM

· Flash ONFI 3.0

· Flash PPM

· Flash Toggle2NAND

· GDDR3

· GDDR4

· GDDR5

· LBA NAND

· LPDDR2

· LRDIMM

· MMC 4.41

· One NAND

· QDR SRA

· SD/SDIO 2.0

· SD/SDIO 3.0

· SDRAM

· SRAM

· SRAM cellular

· Toggle NAND

· Wide I/O SDRAM


























































We have updated the VIP wiki to reflect the strong focus put by Cadence on the VIP products. Unfortunately we are missing a key factor: the weight, in term of revenue, of the VIP market. There is no market survey giving even an evaluation of the $ value of this segment. We have said previously in Semiwiki that “IP would be nothing without VIP” and we have tried to evaluate the size of this segment. The conclusion was it could be anything between $200M to $500M… Not a very precise evaluation, I agree. If anybody wants to challenge it, feel free to post a comment!



That we can say is that Cadence, with the current offer supporting more than 50 protocol standards, will certainly get a strong market share of VIP, maybe in the same range than Synopsys market share in the Interface IP segment (also based on protocol standards or specifications), or about 50% of the segment. If anybody from Cadence wants to comment this assertion, feel free to post a comment!



Eric Esteve from IPnest [post_title] => Yalta in EDA: Cadence stronger in VIP territory… [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => yalta-in-eda-cadence-stronger-in-vip-territory [to_ping] => [pinged] => [post_modified] => 2019-06-14 21:39:35 [post_modified_gmt] => 2019-06-15 02:39:35 [post_content_filtered] => [post_parent] => 0 [guid] => https://35.226.139.164/uncategorized/687-yalta-in-eda-cadence-stronger-in-vip-territory/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 2 [filter] => raw ) [8] => WP_Post Object ( [ID] => 681 [post_author] => 3 [post_date] => 2011-08-06 21:29:00 [post_date_gmt] => 2011-08-06 21:29:00 [post_content] => I've blogged about the Calibre family of IC design tools before:

Smart Fill replaced Dummy Fill Approach in a DFM Flow
DRC Wiki
Graphical DRC vs Text-based DRC
Getting Real time Calibre DRC Results with Custom IC Editing
Transistor-level Electrical Rule Checking
Who Needs a 3D Field Solver for IC Design?
Prevention is Better than Cure: DRC/DFM Inside of P&R
Getting to the 32nm/28nm Common Platform node with Mentor IC Tools

If you want some hands-on time with the Calibre tools then consider attending the August 11th workshop in Irvine, CA.

[post_title] => August 11th - Hands-on Workshop with Calibre: DRC, LVS, DFM, xRC, ERC [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => august-11th-hands-on-workshop-with-calibre-drc-lvs-dfm-xrc-erc [to_ping] => [pinged] => [post_modified] => 2011-08-06 21:29:00 [post_modified_gmt] => 2011-08-06 21:29:00 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/august-11th-hands-on-workshop-with-calibre-drc-lvs-dfm-xrc-erc.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [9] => WP_Post Object ( [ID] => 678 [post_author] => 9491 [post_date] => 2011-08-05 18:04:00 [post_date_gmt] => 2011-08-05 18:04:00 [post_content] =>  SNUG in Silicon Valley was in March so either you were there or you've missed it. But it is the summer (and fall) of SNUG in the rest of the world:

SNUG China (in Beijing, Shanghai, Shenzhen) on August 22nd-30th
SNUG Singapore on August 23rd
SNUG Taiwan (in Hsinchu) on August 25-26th
SNUG Japan (in Tokyo) on September 7th
SNUG Canada (in Ottowa) on September 19th
SNUG Boston on September 29th
SNUG Austin on October 3rd

Full details here.



 [post_title] => SNUG outside Silicon Valley [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => snug-outside-silicon-valley [to_ping] => [pinged] => [post_modified] => 2019-06-14 20:52:49 [post_modified_gmt] => 2019-06-15 01:52:49 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/snug-outside-silicon-valley.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) ) [post_count] => 10 [current_post] => -1 [in_the_loop] => [post] => WP_Post Object ( [ID] => 695 [post_author] => 4 [post_date] => 2011-08-10 10:32:00 [post_date_gmt] => 2011-08-10 10:32:00 [post_content] => If Cadence is making money with large VIP port-folio, Synopsys has successfully deployed an acquisition strategy to build a large Design IP port-folio. Looking at these acquisitions will help understanding Synopsys positioning in the IP market. When they have started this acquisition campaign, back in 2002, their market share was a few % of a market weighting less than $1 Billion…




The first acquisition was InSilicon in July 2002. Synopsys bought IP for interface standards such as USB, PCI, Ethernet, and 1394. This was their first step in the Interface, standard based, IP market and they keep playing in this segment, doing pretty well as they are now the undisputed leader as we will see further in this blog.

Then they have acquired Cascade in October 2004. Cascade, was one of the very first companies involved in the new (at that time) PCI Express protocol. They plaid the game pretty well, their Controller IP being selected by the PCI-SIG as the reference system to be used for testing any new PCI Express system (IP, ASSP or board) during “plugfest”, in order to get the certification. Thus, CASCADE was were very well positioned to enjoy the first sales of PCIe IP, when you can charge for the license a price which is X3 or X4 that it will be a couple of years later! Even if Synopsys had already a design team developing a PCIe Controller (and PHY) IP, acquisition was a quick and efficient way to kill a dangerous competitor, and to jump start in this market with the positive image of an Innovator. At that time the PCI Express IP market, as reported by Gartner, was pretty small. Amazing to notice, three out the four companies ranked in the top 4, Rambus, ARM and Cadence have exited the market in the meantime (2007-2008). Rambus and ARM because it was not on line with their new business model. But Cadence came back in 2010 when they bought Denali, it’s too early to know what will be their success.



In 2007, Synopsys was enjoying business growth –and good market share- in almost every segment of Interface IP: USB, PCIe, SATA, except Memory Controller (DDRn). This market segment was strongly dominated by Rambus and Denali, which make sense as both companies where involved for long time in development around DRAM. As the ASIC market was moving to a SoC market (ASIC + embedded core), the need to integrate a Memory Controller to interface with external DRAM, in a more and more complex manner, was pushing the DDRn Controller IP sales. Once again, Synopsys decided for the faster and easier (providing you have deep pocket) way: they bought Mosaid in July 2007 and get access to the DDRn Controller IP market, which was not so big at that time:





In 2009 they were doing well in every segment of the Interface IP market, so the acquisition of the mixed-signal IP division of MIPS (in fact Chipidea bought in August 2007 for $147 million in cash!) in May 2009 for a mere $22 million was an opportunistic move. First, it brings a large port-folio of mixed signal IP (ADC, DAC and many more), allowing Synopsys to expand the penetration in the IP market, in a segment they have ignored so far. It was also a way to definitely kill any competition in the USB IP market, where they enjoyed already more than 60% market share and ChipIdea/MIPS 26%...




Also to notice, the fact that Chipidea was involved in two recent if not emerging protocols: HDMI and MIPI, even if this was not the reason for buying. This acquisition was just the kind of opportunity you can’t miss, and the reason why MIPS accept such a discounted price had to do with the recession, but also with the fact they didn’t succeed in running a mixed signal IP product line, where every design-in is almost a redesign, completely at the opposite with processor core.

So you could think that it was enough acquisitions. But the next important move on the chessboard came from cadence: they acquired Denali for $315M in May 2010! I am sure (even if I share no secret as I don’t really know it by fact) that Synopsys has to do with this pretty high price (a x7 multiple of Denali revenue), and that they have pushed up the bidding. Nevertheless, Denali was doing very well with DDRn Controller IP, and many analysts propose predictions above $100M for this IP segment. If you look for a way to expand your business by going in a place where you are not (Memory compilers and Libraries), and consolidate your share in DDRn Controller IP, then Virage Logic looks to be the right acquisition to do, and a smart way to answer to Cadence acquisition of Denali, is’n it? That was the last acquisition made by Synopsys, in June 2010. When you look at the DDRn Controller IP market figures for 2009, and when you know that the target was $10M for Virage Logic for 2010, you better understand it, even if adding a $40M to $50M yearly revenue coming from Memory Compilers and Libraries was also part of the equation, but the expected growth for these segments is almost null:




So, acquisition after acquisition, Synopsys has built a wide port-folio including:


and they have a dominant position in each product line. They have also acquired ARCprocessor core product line (through Virage Logic), and they clearly have a weak position here. Moreover, does Synopsys really want to compete with ARM core’s business? I am not sure, but we will see what will happen in the future…

Eric Estevefrom IPnest(a lot more about Interface IP here)






[post_title] => Yalta in EDA: but Synopsys ultra dominant in Interface IP territory… [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => yalta-in-eda-but-synopsys-ultra-dominant-in-interface-ip-territory [to_ping] => [pinged] => [post_modified] => 2019-06-14 20:52:53 [post_modified_gmt] => 2019-06-15 01:52:53 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/yalta-in-eda-but-synopsys-ultra-dominant-in-interface-ip-territory.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [comment_count] => 0 [current_comment] => -1 [found_posts] => 6848 [max_num_pages] => 685 [max_num_comment_pages] => 0 [is_single] => [is_preview] => [is_page] => [is_archive] => [is_date] => [is_year] => [is_month] => [is_day] => [is_time] => [is_author] => [is_category] => [is_tag] => [is_tax] => [is_search] => [is_feed] => [is_comment_feed] => [is_trackback] => [is_home] => 1 [is_privacy_policy] => [is_404] => [is_embed] => [is_paged] => 1 [is_admin] => [is_attachment] => [is_singular] => [is_robots] => [is_posts_page] => [is_post_type_archive] => [query_vars_hash:WP_Query:private] => c4e97ea38c8f09e1138366c0a76a9975 [query_vars_changed:WP_Query:private] => [thumbnails_cached] => [stopwords:WP_Query:private] => [compat_fields:WP_Query:private] => Array ( [0] => query_vars_hash [1] => query_vars_changed ) [compat_methods:WP_Query:private] => Array ( [0] => init_query_flags [1] => parse_tax_query ) [tribe_is_event] => [tribe_is_multi_posttype] => [tribe_is_event_category] => [tribe_is_event_venue] => [tribe_is_event_organizer] => [tribe_is_event_query] => [tribe_is_past] => )

Yalta in EDA: but Synopsys ultra dominant in Interface IP territory…

Yalta in EDA: but Synopsys ultra dominant in Interface IP territory…
by Eric Esteve on 08-10-2011 at 10:32 am

If Cadence is making money with large VIP port-folio, Synopsys has successfully deployed an acquisition strategy to build a large Design IP port-folio. Looking at these acquisitions will help understanding Synopsys positioning in the IP market. When they have started this acquisition campaign, back in 2002, their market shareRead More


Speeding Verification of FPGA Prototype Boards

Speeding Verification of FPGA Prototype Boards
by Paul McLellan on 08-09-2011 at 5:42 pm

It is no secret that SoC designs continue to increase in complexity and time-to-market windows are shrinking. While there is room for debate on just how big a fraction of SoC design effort goes on verification, there is no debating that it is a large part of the total. Simulation is increasingly too slow, especially when software … Read More


Smartphones shipments, Sky is the limit…

Smartphones shipments, Sky is the limit…
by Eric Esteve on 08-08-2011 at 8:50 am

…or a global recession, but that’s not the purpose of this blog. As everybody knows, Apple is designing and selling smartphones, only. Does it mean that only smartphones are generating profit in the mobile industry? As we have seen recently in Semiwiki, Apple makes 2/3 of profit of entire mobile industry.

Let’s have a look (below)… Read More


Samsung to Acquire AMD?

Samsung to Acquire AMD?
by Daniel Nenni on 08-07-2011 at 4:00 pm


Don’t get me wrong, I’m a big fan of AMD, I buy AMD based products whenever possible to prevent an innovation stifling Intel monopoly. Unfortunately Silicon Valley coffee house conversations continue to paint a bleak picture for AMD, even with a recent stock surge on better than expected revenue guidance for the rest of 2011. I… Read More


Sentinel-PSI Webinar

Sentinel-PSI Webinar
by Paul McLellan on 08-07-2011 at 3:28 pm

The last of the current series of webinars is on Sentinel-PSI,IC-Package, Power and Signal Integrity Solution. It will be at 11am Pacific time on Thursday 11th August. It will be conducted by Dr. Tao Su, product manager of the Sentinel products. Dr. Su has many years of experience in the EDA industry and is specialized in power integrity… Read More


Apple Roadmaps Intel to 14nm

Apple Roadmaps Intel to 14nm
by Ed McKernan on 08-07-2011 at 1:11 pm

Intel will not win the tablet market with any of the various Atom chips rolling out at 32nm, 22nm and even 14nm. They are too late to a game that Apple owns 90% of today and will so in the future. All of these ultra low power atom versions are like the Saturn test rocket developments that preceded the Apollo 11 Moon Landing. They are necessary… Read More


Yalta in EDA: Cadence stronger in VIP territory…

Yalta in EDA: Cadence stronger in VIP territory…
by Eric Esteve on 08-07-2011 at 5:42 am

…when Synopsys is getting the lion’s share in Interface IP. In Q2 2010, there was two major acquisitions in EDA world: Synopsys has bought Virage Logic (for more than $300M) when Cadence bought Denali for an equivalent amount. Synopsys bought a 100% IP focused company, when Cadence bought a strongly VIP focused company. Does it … Read More


August 11th – Hands-on Workshop with Calibre: DRC, LVS, DFM, xRC, ERC

August 11th – Hands-on Workshop with Calibre: DRC, LVS, DFM, xRC, ERC
by Daniel Payne on 08-06-2011 at 9:29 pm

I’ve blogged about the Calibre family of IC design tools before:

Smart Fill replaced Dummy Fill Approach in a DFM Flow
DRC Wiki
Graphical DRC vs Text-based DRC
Getting Real time Calibre DRC Results with Custom IC Editing
Transistor-level Electrical Rule Checking
Who Needs a 3D Field Solver for IC Design?
Prevention is BetterRead More


SNUG outside Silicon Valley

SNUG outside Silicon Valley
by Paul McLellan on 08-05-2011 at 6:04 pm

SNUG in Silicon Valley was in March so either you were there or you’ve missed it. But it is the summer (and fall) of SNUG in the rest of the world:

SNUG China (in Beijing, Shanghai, Shenzhen) on August 22nd-30th
SNUG Singapore on August 23rd
SNUG Taiwan (in Hsinchu) on August 25-26th
SNUG Japan (in Tokyo) on September 7th
SNUG … Read More