Interview with David Tester VP of Engineering Mach42David Tester is the VP of Engineering at…Read More
The $725 Million Chip Development: Why Execution Risk, Not IP Cost, Now Dictates Advanced-Node SurvivalThe philosophy of relying on a single, unified…Read More
CTO Interview with Taylor Barton of Certus SemiconductorTaylor Barton is a Lead Analog/Mixed-Signal and I/O…Read More
Generating Chip Subsystems Automatically: A New Answer to Manage Chip Design Complexity By Defacto Staff Today’s chips are no longer…Read More
Reimagining 3D IC Design: From Architecture to SignoffBy Keith Felton, Andras Vass-Varnai and Todd Burkholder,…Read More
When you think of Indian music you might think of ragas for the sitar. But when you think of Indian MUSIC, that is the Magma user group meeting (Magma Users Summit for Integrated Circuits) coming up on September 7th in Bangalore (note: the date has changed from when it was originally announced). It is at Vivanta by Taj on M G Road.
There… Read More
Atrenta has four seminars coming up on SoC realization. More and more design is actually about finding IP and integrating it together at the block level, and then handing it off to a standard RTL to GDSII flow. The three focus areas are:
Next Tuesday, August 23rd, is the ANSYS Regional Conference for Silicon Valley. It takes place at the Techmart Network Meeting Center. Apache has three presentations during the day:
Mr. TTL (otherwise known as Texas Instruments or TI) has had a great run in the cellular market but it is time to decamp. The future is Analog and OMAP must depart to one of the remaining players looking to win the Smartphone and Tablet market. TI is exiting the market so it can focus on the high volume analog market.
On first sight, the … Read More
Call me Ishmael. Some years ago –in the mid 1990s – having little or no money in my purse and nothing particular to interest me on shore, I thought I would sail the startup ship Cyrix and see the watery part of the PC world. Whenever I find myself grim about the mouth or pause before coffin warehouses, and bring up the rear of every funeral… Read More
Introduction
When I designed DRAM chips at Intel I wanted to simulate at the worst case process corners to help make my design as robust as possible in order to improve yields. My manager knew what the worst case corners were based on years of prior experience, so that’s what I used for my circuit simulations.… Read More
First, I would like to congratulate Samsung on their first 20nm test chip press release. Some will say it is a foundry rookie mistake since real foundries do not discuss test chip information openly. I like it because it tells us that Samsung is 6-9 months BEHIND the number one foundry in the world on the 20nm (gate-last HKMG) process… Read More
So Google is buying Motorola Mobility for $12.5B. If you are a partner of Google using Android then this has both upside and downside. The upside is that Motorola, having been in wireless for longer than almost anyone, presumably has a pretty good patent portfolio that can be used to defend against Apple, Nokia, Microsoft et al. The… Read More
If you did not have the chance to attend the famous Denali party at DAC 2011, you may want to go to Cadence VIP seminar to be held on Thursday, August 25, 2011, from 1:00 – 4:15pm at Cadence Headquarters: 2655 Seely Avenue, San Jose, Building 10. To register, click here. The atmosphere could be slightly different, as during Denali… Read More
Wyatt Earp probably wasn’t thinking of OPC when he said, “Fast is fine, but accuracy is everything,” but I’ll adopt that motto for this discussion of full-chip OPC and post-OPC verification models.
Accuracy is the difference between the calibrated model prediction and the calibration wafer result. Accuracy depends on several… Read More
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The $725 Million Chip Development: Why Execution Risk, Not IP Cost, Now Dictates Advanced-Node Survival