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Jumpstart your testbench development with Questa Verification IP
August 21, 2019
Register For This Web Seminar
11:30 AM – 12:30 PM US/Eastern
Hosted by Oasis Sales and Trilogic, Inc.
Today’s designs rely heavily on a growing variety of complex industry standard interfaces. Confections to these interfaces must be verified to ensure IP interoperability and correct system behavior. Mentor’s verification IP (VIP) improves quality and reduces schedule times by building Mentor’s protocol and methodology expertise into a library of reusable components that support many industry standard interfaces. This frees up engineering resources from having to spend time developing BFMs, verification components, or VIP themselves, enabling them to focus on the unique and high-value aspects of their design.
Who Should Attend
- Verification engineers
- Verification managers
Walter GudeWalter has over 25 years of experience in ASIC/FPGA design and holds a MS in Electrical Engineering from Washington University in St. Louis. He worked for 6 years doing ASIC design at Tellabs Operations. From there, he went to work for Mentor Consulting where he consulted on various ASIC projects including time spent in Munich Germany and Helsinki Finland. For the last decade, Walter has worked as an Application Engineer supporting Mentor’s line of Functional Verification Projects.
What You Will Learn
- Rapidly generate verification IP components most common protocols use in UVM testbench environment
- Use built in sequence items quickly create transaction on your protocol bus
- Use built in transaction streams to view transactions in the wave window, raising abstraction level of debug
- Identify critical protocol features and use VIP sequences and coverage to verify testing of these features
- Rapidly generate memory models and quickly integrate them into any testbench using Mentor’s memory configurator software
- Verify your memory controllers with assertions, coverage, and transaction level debug