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MZ Technologies Enables Multi-Die Design with GENIO

MZ Technologies Enables Multi-Die Design with GENIO
by Mike Gianfagna on 04-01-2024 at 6:00 am

MZ Technologies Enables Multi Die Design with GENIO

MZ Technologies is a unique company that enables multi-die design by providing critical planning and analysis tools that sit above the traditional EDA design flow. Chip and package design tools are good at what they do. Given a set of constraints, they will deliver a good result. The question is, what is the right set of constraints?  What type of stack (for 3D), what type of interposer (for 2.5D) and what type of placement of blocks and pins will deliver the best result?  These are just some of the questions MZ Technologies addresses. The company’s design tool is called GENIO™. I got an opportunity to see a live demonstration of the tool recently. That illuminated a lot about its impact. Read on to see how MZ Technologies enables multi-die design with GENIO.

If you want some background on MZ Technologies and how its products fit in the design flow, you can get that here.  You can also get an overview of the GENIO product suite here. As they say, a picture is worth 1,000 words. A live demo has similar power to illuminate concepts. Let’s dig in…

GENIO for 2.5D

Francesco Rossi
Francesco Rossi

Francesco Rossi, engineering manager at MZ Technologies began the demo by developing a 2.5D design consisting of an XPU and four HBM memory stacks. Using simple and intuitive “drag and drop” capabilities and library managers, he configured items such as the four HBM stacks, the XPU, the PHYs for each HBM and a silicon interposer.  Bump locations were also defined for the interposer to handle connectivity between components and through the silicon interposer to the package substrate. Connection points on the package were also defined with GENIO in a straight-forward manner.

Below is a screen shot of the graphical representation of the completed stack.

2.5D Stack Configuration
2.5D Stack Configuration

Once the complete stack was defined (package, interposer, devices), connectivity was introduced and optimized. The optimization process examined the fly lines implied by the connectivity to minimize overall fly line length. This will deliver a more optimal starting point for the downstream implementation flow. Consideration was also given to ensure there were no crossovers in the fly lines. The figure below shows the results of this work. All fly lines are displayed. The red items are through-silicon vias (TSVs). These have been either automatically placed or guided by the designer for critical areas.

2.5D Stack with Fly Line Routing
2.5D Stack with Fly Line Routing
Anna Fontanelli
Anna Fontanelli

Anna Fontanelli, founder and CEO at MZ Technologies also joined the demo. She explained that this demo was developed in conjunction with Synopsys to ensure a good fit between GENIO and the implementation tools and IP that it works with. She said that Synopsys DesignWare IP was used for the demo, which interfaced with Synopsys IC Compiler and Custom Compiler. The key point was a good flow between the high-level planning offered by GENIO and the tools and IP that would ultimately implement the final system.

She went on to explain that this design had over 200,000 nets. The interconnect cockpit provided by GENIO delivers substantial new capabilities to manage and optimize a problem of this size. For example, pin groupings can be defined that cross the entire design hierarchy. Fly lines and group of fly lines can be analyzed for average, min and max length. She pointed out that analyzing the design across the full hierarchy, from silicon all the way to the package provides a unique perspective on system performance that is difficult to achieve with conventional approaches.

Using these, and many other capabilities the aspect ratio of the initial design can be examined to ensure an optimal result. Slight changes in aspect ratio and placement can be quickly assessed to find the best result. Anna also explained that estimated resistances can be extracted from the interconnect to drive early static timing analysis.

GENIO for 3D

Marco Cignarella
Marco Cignarella

Marco Cignarella, senior software engineer at MZ Technologies showed how GENIO can be used to define and optimize 3D stacks. A design consisting of multiple chips and memories was used. By changing the stack configuration, the overall interconnect length and number of TSVs can be quickly assessed. Key relationships about the relative placement of components in the 3D stack can be easily specified before optimization begins. This allows global designer perspective to be considered with minimal intervention.

Using these capabilities, the top two or three stack configurations can be quickly identified for further analysis. Below are screen shots of one candidate 3D stack configuration and the associated fly line routing view. A lot of global perspective can be achieved in a short period of time.

3D Stack Configuration
3D Stack Configuration
3D Stack with Fly Line Routing
3D Stack with Fly Line Routing

To Learn More

This demo session provided an incredible amount of design perspective and analysis in a short period of time. I am sure many design teams work to develop the optimal configuration for a 2.5D or 3D design using Microsoft Excel and PowerPoint. The data that drives these analyses is often scattered across multiple directories.

The ability to do this work in one “cockpit” with one, verified data source and automated analytics and visualization tools can take a multi-week project down to a day or so, with far better results. If you are considering multi-die design, you need a tool like GENIO. The ways to contact MZ Technologies can be found here. And that’s how MZ Technologies enables multi-die design with GENIO.

Also Read:

MZ Technologies Enables Multi-Die Design with GENIO

How MZ Technologies is Making Multi-Die Design a Reality

Outlook 2024 with Anna Fontanelli Founder & CEO MZ Technologies

CEO Interview: Anna Fontanelli of MZ Technologies

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