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SemiWiki WEBINAR: eFPGA – what a great idea! But I have no idea how I’d use it!

August 20 @ 10:00 am - 10:45 am

Multiple Webinar Times Available

Tuesday, August 20, 2019, @ 10:00am (PDT) – San Jose, CA
Wednesday, August 21, 2019, @ 10:00am (CST) – Shanghai, China
Wednesday, August 21, 2019, @ 10:00am (CEST) – Munich, Germany

Please select the correct webinar for you time zone on the registration page.

Overview

For decades, chip designers have thought wouldn’t it be great to have RTL flexibility for their ASICs. Decades have come and gone and there have been many failed attempts at providing this type of technology. Now that there is viable, usable FPGA IP available for designers, the challenge now is up to the designer to take advantage of it. This webinar is to discuss why FPGA IP is viable now and provide some ideas for designers where they may be able to take advantage of this programmable technology on their next ASIC.

What You Will Learn

Scenarios and methods for using eFPGA embedded FPGA hard IP and with its related software. How eFPGA provides added flexibility in critical areas where a customer’s or market’s needs are changing.

Who Should Attend

  • Chip Architects
  • SoC design engineers and managers
  • Semiconductor engineering executives

More details can be found on the registration page here.

*** This vendor requires that you register with your work email address. ***
*** This webinar will be given at three different times. The registration page can show webinar times in your time zone for you to choose from. ***

Details

Date:
August 20
Time:
10:00 am - 10:45 am