WEBINAR: Silicon Area Matters!

When designing IP for system-on-chip (SoC) and application-specific integrated circuit (ASIC) implementations, IP designers strive for perfection. Optimal engineering often yields the smallest die area, thereby reducing both cost and power consumption while maximizing performance.

Similarly, when incorporating embedded FPGA (eFPGA) IP into a SoC, designers prioritize these critical factors. eFPGA IP is inherently scalable, enabling it to be tailored to each customer’s specific requirements. However, the necessary FPGA logic is not only determined by the programmed design, but also by the compiler and FPGA architecture used.

Embedded FPGA provides crucial flexibility, allowing SoCs to adapt to changing standards, protocols, customer requirements and post-quantum cryptography algorithms as well as enables software acceleration and deterministic processing. Flex Logix’s EFLX eFPGA architecture delivers industry-leading performance, power, and area (PPA) metrics. It features a familiar 6-input lookup table (LUT) along with a highly efficient, patented routing switch matrix that sets it apart from competitors. This switch matrix reduces the number of metal stack layers, enabling EFLX to meet the stringent requirements of edge IoT devices.

Recently Flex Logix announced the availability of eXpreso, its powerful 2nd generation EFLX eFPGA compiler and successor to the first-generation compiler, EC1.0. eXpreso, which has been in development for years, is now shipping to alpha customers for evaluation. The new compiler delivers up to 1.5x higher frequency, 2x denser LUT packing and 10x faster compile times for all existing EFLX tile and arrays. Now IC designers can further reduce eFPGA IP implementation to levels never seen before.

REPLAY: Reconfigurability is now achievable with significantly reduced silicon area, thanks to new Flex Logix eFPGA compiler

Abstract:

Many IC architects value the adaptability and reconfigurability of embedded FPGA (eFPGA) technology, but often dismiss it due to the implementation cost. Their focus on smaller die area and power consumption are primary drivers. Flex Logix has addressed this challenge with its new, game-changing eFPGA compiler tool, eXpreso, which can dramatically decrease the required die area impact of adding eFPGA. eXpreso’s innovative routing optimizations and packing ability can cut design implementations in half.

This webinar will provide an opportunity to learn more about Flex Logix’s embedded FPGA IP and problem-solving applications, and to see a live demonstration of eXpreso and how it can significantly reduce the area of embedded FPGA IP.

Presenters:

Jayson Bethurem – VP, Marketing & Business Development
Jayson is responsible for marketing and business development at Flex Logix. Jayson spent six years at Xilinx as Senior Product Line Manager, where he was responsible for about a third of revenues. Before that he spent eight years at Avnet as FAE, showing customers how to use FPGAs to improve their products. Earlier, he worked at start-ups using FPGAs to design products.

Brian Philofsky – Sr Director of Solutions Architecture
Brian is Sr Director of Solutions Architecture supporting customers in their technical evaluation and implementation of Flex Logix Hardware and Software. Brian spent more than 25 years at Xilinx/AMD in various roles including Director of Technical Marketing, Principal Engineer for Power Solutions, and managing applications, design services and support roles. Brian has been awarded 13 US Patents.

About Flex Logix

Flex Logix is a reconfigurable computing company providing leading edge eFPGA, DSP/SDR and AI Inference solutions for semiconductor and systems companies. Flex Logix eFPGA enables volume FPGA users to integrate the FPGA into their companion SoC, resulting in a 5-10x reduction in the cost and power of the FPGA and increasing compute density which is critical for communications, networking, data centers, microcontrollers and others. Its scalable DSP/SDR/AI is the most efficient, providing much higher inference throughput per square millimeter and per watt. Flex Logix supports process nodes from 180nm to 7nm, with 5nm, 3nm and 18A in development. Flex Logix is headquartered in Mountain View, California and has an office in Austin, Texas. For more information, visit https://flex-logix.com.

Also Read:

Flex Logix at the 2024 Design Automation Conference

Elevating Your SoC for Reconfigurable Computing – EFLX® eFPGA and InferX™ DSP and AI

WEBINAR: Enabling Long Lasting Security for Semiconductors