Free Webinar on Verifying On-Chip ESD Protection

Walking across a carpet can generate up to 35,000 volts of static charge, which is tens of thousands of times higher than the operating voltages of most integrated circuits. When charge build up from static electricity is exposed to the pins of an IC, the electrostatic discharge (ESD) protection network on the chip is intended to harmlessly shunt the current to ground. Decades of design experience have taught us how to design these protections. However, if the ESD protections are not properly implemented on chip, or if there is a design flaw, such as incorrect design parameters, a chip can fail in the field. ESD related failures can be instantaneous when they are caused by things like a device burnout, or they can be slow when they are caused, for instance, by electromigration (EM).

An ESD failure in the field can be expensive and can even lead to safety issues, depending on the end product application. The best way to ensure that ESD protections, as implemented, are going to prove effective is to verify them in layout prior to tape out. Waiting until testing can waste time and money, and lead to difficulties in identifying the root cause of the problem. Fortunately, there is a way for IC designers to verify the ESD protections on a chip once the layout is available.

Magwel offers its ESD protection network verification tool ESDi to rapidly detect a wide range of design and implementation issues that can lead to ESD failures. ESDi can check for unprotected pins, missing vias, missing or undersized ESD devices, high bus resistance and more. It also uses parallel processing to quickly simulate HBM events on all or a subset of the pin pairs on a chip. The simulation uses TLP models and can accurately model snap back behavior. It can also predict competitive triggering of multiple ESD devices in a single ESD event. ESDi will report current density and EM violations.

Error and violation review is made easy with an advanced user interface for filtering, sorting and selecting errors to view in detail and visualize their locations. False or missed errors are dramatically reduced by using simulation for all tests, instead of having the user pick and choose what potential issues need simulation.

To give a firsthand look at how ESDi is set up and used, Magwel is offering a free webinar on Tuesday June 9^th at 10AM Pacific Time. In this webinar Magwel Application Engineer Allan Laser will provide an overview of the tool’s features followed by running a sample design so viewers can better understand each step of operation.

ESDi can be used at the block or chip level. It has its own simulator specifically optimized for ESD event modeling and also has a high accuracy solver-based extractor for use on the design layout. ESDi also has automated and simplified the process of ESD device identification.

ESDi is remarkably effective because its development was based on customer input. The webinar will provide a glimpse into the many large and small features in the tool that make it the choice for many leading semiconductor companies. Registration for the webinar replay of Magwel’s ESDi is available here.

About Magwel
Magwel® offers 3D field solver and simulation based analysis and design solutions for digital, analog/mixed-signal, power management, automotive, and RF semiconductors. Magwel software products address power device design with Rdson extraction and electro-migration analysis, ESD protection network simulation/analysis, latch-up analysis and power distribution network integrity with EMIR and thermal analysis. Leading semiconductor vendors use Magwel’s tools to improve productivity, avoid redesign, respins and field failures. Magwel is privately held and is headquartered in Leuven, Belgium. Further information on Magwel can be found at www.magwel.com