Design Data Management: An Analog IP Porting Case Study

IQ-Analog Corp. offers “off-the-shelf” data converter intellectual property (IP) for multiple foundries. The San Diego, California–based semiconductor design firm also provides analog front-end (AFE) technology that it tailors according to customer needs. And that’s where the dilemma begins.

IQ-Analog’s customers have different requirements, and they use different foundries and manufacturing processes. For a start, the IP products that IQ-Analog delivers requires customization for a new fab and technology node. They also require back end of line (BEOL) metal stack variations. Furthermore, IQ-Analog has to customize IPs in a tight delivery schedule while leveraging the existing designs.

Then, there are analog IP porting challenges regarding the availability of similar active and passive components. And different BEOLs and DRC rules lead to manual physical layout modifications. Inevitably, these design updates and verification iterative cycle result in project delays.

Data management tools allow to pick a coherent set of changes

According to Dan Woodard, Director of Operations at IQ-Analog, IC design changes happen on multiple axes, and we need to pick these changes from multiple lines of development. “These changes are dynamic with a number IC designers operating on the same data, so we need to reliably select a coherent set of changes.”

Analog IP Porting: The Solution

Woodard took the floor at the 52nd Design Automation Conference (DAC) and shared the details of the solution that has worked well for his company. He told the DAC audience that IQ-Analog couples EDA tools to data management tools to keep track of various versions of IP content, including schematics, layout, simulation setups, technology kits, etc.

That helps the design firm leverage the use of an organized library with numerous tags and branches and assemble the targeted IP core. The combo of EDA and data management tools specifically helps IQ-Analog address customer requirements as the company can clearly establish the project configuration to efficiently leverage its ever-growing library of IP content without redundancies.

Dan Woodard speaking at DAC’s IP Track

IQ-Analog, which uses ClioSoft’s SOS data management platform, follows a strict rule-based system using tags and branches. Tags are employed to mark meaningful development milestones while branches are used to represent alternative development paths. The tagging feature in SOS allows labeling a revision with a meaningful name so that a revision of a file can have multiple tags and a tag on a file can be moved to a different revision.

Next up, the branching feature provides the ability to create an alternative path of development. Sub-branches can be created off branches. Moreover, all branches of development are visible to all design project team members, allowing changes on multiple branches to be selected.

ClioSoft’s SOS data management platform also provides revision search order (RSO) feature, a priority ordered list of tag and branch names, which serves as a rule to pick revisions to create a workspace. Here, revision with the first matching tag or branch name is selected.

ADC Case Study

IQ-Analog’s Woodard presented analog-to-digital converter (ADC) as an example of how analog IP is ported to a chip design. An ADC cell has a poly resistor component for which initial implementation is carried out by creating libraries for all anticipated fabs. These libraries are segregated by branches and tags.

ADC sub-component example

“If we want to move to a new fab, we simply update the RSO with the new reference libraries,” Woodard said. “The updated resistor now references the proper cell for the new fab.” He further explained how an IP product containing resistors, capacitors and related analog components is migrated from TSMC 40nm process to GlobalFoundries 40nm process in just two weeks.

The library has a built-in capability of rapid transition and can move from one foundry technology to another without carrying out the layout work twice. Woodard also showed how retargeting from TSMC’s 40nm BEOL of 5x2x to 6x2z takes just two days. “IQ-Analog was able to maintain TSMC branch and only branched further the layout views in which the metal transitioned above the thin metals.”

The Net effect

IQ-Analog’s Woodard told the DAC crowd that a design data management tool like ClioSoft’s SOS allows IC designers to augment only a few items to implement a fix rather than traversing all implementations to incorporate fixes and corrects. “Changing the underlying reference and then re-running verification may be all that is needed for delivery.”

Analog IP migration from one fab to another

He also acknowledged the value of using data management tools that comes with the automation of the process; it allows IQ-Analog to reduce the time required to map an analog IP from one foundry node to another.

The upfront work of creating the content in a given node facilitates an IC designer to implement fixes in all the nodes instantly, saving the time it would take to implement the changes uniquely in each project. “The automation enabled by tools like SOS design data management platform avoids clerical errors that can be manually introduced in mapping from one node to another,” Woodard concluded.

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