How Emulation Enables Complex Power Intent Modeling

As the number of CPU, GPU, and IP is growing in an SoC, power management is becoming more and more a complex task in itself. A single tool or methodology may not be enough for complete power management and verification of an SoC. In an SoC, there can be multiple modes of operations involving hardware and software interactions, different applications running, and complex dynamic power profiles of those applications. One key aspect is power intent modelling and verification. The power intent is described in CPF (Common Power Format) or UPF (Unified Power Format) files. The design has to honour the rules described in these files and work properly even when certain parts of the design are inactive or in sleep mode.

Broadly speaking, the UPF files contain descriptions about components such as switches, level shifters, isolation cells, and retention cells. These files can be best used by different verification tools including simulation and emulation under different situations. Emulation has been a unique verification method for real world testing. AMDhas been using In-Circuit Emulation (ICE) for its GPU (Graphics Processing Unit) and APU (AMD Accelerated Processing Unit) power modelling and verification. GPU is a simpler case in which the GPU resides inside Cadence’sPalladium system and is divided into multiple power domains. A test PC is connected to the GPU through a PCIe speed-bridge. The test PC is also connected to a debug PC through fire-wire. The switching of power domains is dynamically controlled by hardware and software. The main purpose is to keep the Power dissipation of the overall GPU low. The APU is more complex than GPU; an example is below.

Inside the emulator, the power domains are shown in orange color. There are many power domains in the Graphics & Multimedia Engine and other units which need extensive power management with many complex power scenarios to test. There are multiple CPU cores. There is a separate CPU for system management and security. There are power safe operations in I/O subsystem and system management units which need to be unified. The Operating System (OS) and test system are on a separate hard disk sitting outside the emulator and connected with it through SATA speed-bridge.

In such a scenario emulation is the most powerful method to test the APU in real world with real use-cases. The application and OS level testing is nearly impossible with the usual simulation method. Dynamic Frequency and Voltage Scaling (DFVS) is a powerful technique to reduce power dissipation by independently scaling frequency and voltage in each power domain. However it requires a significantly complex system management, because in larger and faster chips there can be multiple clock domains to propagate clock signals across the chips. Such a system can be best tested with emulation in real life scenario for best accuracy.

AMD uses UPF 2.0 with all construct level support and the latest UPF 2.1 with semantic level support in Palladium emulation system. Memory scrambling test has been automated with UPF directives which describe about the power domain where the scrambling takes place. With waveform support for objects one can see the states of power related objects. With SDL trigger support in UPF, Palladium can create dynamic triggers on any power related object in the design to put it on or off. This is a unique and powerful feature for power safe transitions.

AMD has a very balanced approach of selecting tests which needs to be run on simulation or emulation. Usually, long running directed tests and those that do not require complex testbench interaction are run on UPF enabled emulation. The pre-silicon emulation workloads comprise power management, BIOS, firmware, OS, and application level workloads. In emulation multiple passes of power sequences can be done as against a single pass in simulation. This enables complex interaction scenarios and repeated power state entry or exit with variable external stimulus.

The APU based testbench can be simplified by connecting a system model with the design in the Palladium system through transactors.

The system model can be in C++. The executing code communicates with the system model where a power event request can be sent to the system model and the system model responds accordingly. This scheme is configurable and aligns uniquely with AMD’s RTL simulation methodology.

This emulation methodology at AMD has proved to be very effective reducing long simulation runtimes drastically. Complex SoC power interactions and closer to real life workloads can be possible through emulation. The runtime failures can be detected through self checking stimulus and power based assertions instrumented into the emulation build.

Alex Starr from AMD presented in detail about this methodology at 52[SUP]nd[/SUP] DAC. The same presentation has been posted HERE with the title “Experiences with SoC Deployment of Hardware Emulation Based Power Intent Modeling”. There is no registration required.

Pawan Kumar Fangaria
Founder & President at www.fangarias.com