May want to listen up; Qualcomm are going to be sharing how they do this. There is a constant battle in designing for low power; you don’t accurately know what the power consumption is going to be until you build it, but by the time you’ve built it, it’s too late to change the design. So you have to find methods to estimate power early on, while using that information in a way that won’t compromise your design choices because you were judging their impact based on eyeballed numbers.
This can appear difficult, particularly for RTL-based power estimation, which typically shows variance of around 15% on final gate-level estimates. Surely judging optimizations based on such coarse estimates would be very challenging unless the changes deliver massive advantages, greater than that margin of uncertainty?
In fact the picture is much better if you do differential analysis – comparing the difference in predicted power savings for different optimizations. While absolute power estimates carry that larger level of uncertainty, differences between estimates can be much more accurate for a fairly obvious reason. Differences subtract out many of the unknowns in absolute RTL power estimates: detailed cell and designware mapping, placement, routing, clock tree details and so on. What you’re left with can be much closer to equivalent differences based on signoff power numbers.
The people who build mobile solutions know more than almost all of us about squeezing out every last pico-watt of power. Apple isn’t likely to tell you what they do, but Qualcomm is just as good for learning about best practices in this domain.
Register HERE to learn more in this webinar on August 23[SUP]rd[/SUP] at 9am PDT
Mobile devices demand high performance in a very constrained environment. As a leader in perf/watt, Qualcomm® Adreno™ GPUs, a product of Qualcomm Technologies, Inc., leverages many effective methods to improve power efficiency. In this regard, Qualcomm has developed a differential energy analysis methodology based on ANSYS PowerArtist to identify the power optimization opportunity in GPU. This methodology can help to locate the inefficient part that needs further optimization in the pre-silicon stage. Experimental results based on identifying unnecessary register toggles demonstrate the effectiveness of this proposed methodology.
Preeti Gupta, is head of RTL product management, for the ANSYS semiconductor business unit.
Yadong Wang is currently a staff engineer in the GPU system power team at Qualcomm Technologies, Inc., San Diego, California. He has about 10 years of ASIC low-power design experience. At Qualcomm, he is responsible for power modeling and analysis of Adreno™ GPUs, and explores and develops many effective methods to improve power efficiency. Before joining Qualcomm, he worked as a hardware power engineer at NVIDIA. Yadong earned an M.S. degree in electrical engineering from Tongji University (Shanghai, China) in 2009.
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