Paving the Path for Robust Electronic System Design

In today’s era of low power and high performance components, preferably on a single chip provides impetus to much larger electronic systems packaged into much smaller cases; smartphones are the immediate examples which encapsulate multiple functions other than the intended ones, viz. phone and data communication. As an example, a smartphone today performs complete function of video recording, viewing and displaying, what a handy-cam was doing a couple of years ago. So you can imagine, doing a live video conferencing or watching a complete movie on a smartphone is not a big deal. The same kind of phenomenon is happening in other applications such as medical, aerospace and automotive; electronics packed into compact spaces to be operated efficiently and conveniently with continuous supply of power and without any break over long duration of operation or any major heat up.

So, how does that happen? One may say it’s not a rocket science. But one must say it’s a science to save those rockets from electronic malfunctioning; most of the systems are controlled by MCUs in electronic boards. The robustness of electronic systems in terms of power consumption, noise, power and signal integrity, EM Interference, electro-thermal, electromigration and electrostatic discharge must be looked at with an integrated approach from bottom up, i.e. dies of chips, their packages and complete systems including PCBs. These days most of the electronics is driven by semiconductors and that means accounting for newer and newer physical effects at nano-meter process nodes like 28nm and 14nm, operating at much reduced voltages and narrow margins for various kinds of noises. That’s science giving rise to robust electronic engineering!

This reminds me about Apache’smerger with Ansys. While Ansys is leading the system design and engineering space solving mechanical, electro-magnetic, electro-mechanical, fluid dynamics and other multi-physics problems for large systems, Apache pioneers in semiconductor IC power optimization, noise and reliability solution at chip, package and system level. It’s a perfect merger integrating the two spaces which complement each other in most respects. In coming days, we will see further closer interaction between the electronic & electrical engineering and the semiconductor space.

The trigger to my mind about this thought was an articleposted by Yukari Ohno about a success story of Ansys’s chip-package-system (CPS) co-simulation solution used by LSI(Avago Technologies) in establishing a robust verification methodology and evaluating and selecting the best package design (that supplied the cleanest power with least noise) for their storage and networking chips. With a single simulation environment for complete chip and package, the chip-package routing was designed to identify and eliminate the noise due to DDR I/O switching activity on PLL supply. The author of the article is Cornelia Golovanov of LSI Corporation. I remember attending her webinar based on this design and development activity at LSI. The details of that study and development are put up here in this article, a must read to understand and appreciate the context of IC/SoC integration into package and system for robust electronic design. Consider the same smartphone example; all those operations can be possible only when there is sufficiently large, efficient, low-power, low-noise, and low-latency and durable storage mechanism in place.

Going back to the initial days of the CPS co-simulation solution introduced by Apache when I had watched an interesting youtube video, to my pleasant surprise, I found it is still there intact. It’s a 2 minutes video that tells about the CPS system which allows seamless communication between chip, package and system engineers to improve overall power and reliability. It’s a real progress happening since then.

RedHawk is an industry standard IC Power Integrity and sign-off solution and Sentinel is a high capacity, high performance chip, package and PCB co-design and sign-off solution. Both work hand-in-hand enabling IC aware system power analysis as well as package aware IC power analysis.

It’s a perfect environment that brings the chip, package and system worlds together. Going forward in future, are we going to see more such mergers between large system design companies and semiconductor design automation companies?

More Articles by Pawan Fangaria…..