Checklist to Ensure Silicon Interposers Don’t Kill Your Design

Traditional methods of chip design and packaging are running out of steam to fulfill growing demands for lower power, faster data rates, and higher integration density. Designers across many industries – like 5G, AI/ML, autonomous vehicles, and high-performance computing – are striving to adopt 3D semiconductor technologies that promise to be the solution. The tremendous growth in 2.5 and 3D IC packaging technology has been driven by high-profile early adopters delivering high bandwidth and latency products.

Benefits of 2.5 and 3D Technology

This trending technology meets the demands of enclosing all functionality in one sophisticated IC package, enabling engineers to meet aggressive high-speed and miniaturization goals. In 3D-IC packaging, dies are stacked vertically on top of each other (e.g. HBM), while 2.5D packaging places bare die (chiplets) next to each other. The chiplets are connected through a silicon interposer and through-chip vias (TSVs). This makes for a much smaller footprint and eliminates bulky interconnects and packaging which can significantly impede data rate and latency performance. Heterogenous integration is another benefit of silicon interposers, enabling engineers to place memory and logic with different silicon technologies in the same package, reducing unnecessary delays and power consumption. Integrating different chips designed in their most appropriate technology nodes provides better performance, cost, and improved time to market when compared to monolithic SOC designs on advanced technology nodes. Monolithic SOCs take longer to design and validate, contributing to increased cost and time to market.

The implementation of silicon interposers allows for more configurable system architectures but also poses additional multiphysics challenges like thermal expansion and electromagnetic interference along with fewer design and production issues.

Challenges of 2.5 and 3D Design

Silicon interposers is a successful and booming advancement in IC packaging technology. This technology will soon replace the traditional methods of chip design. Combining different functional blocks and memory within the same package provides high speed and improved performance for advanced design technologies. But the new considerations with interposers impose unfamiliar challenges and designers must understand the power integrity, thermal integrity and signal integrity interactions between the chiplet dies, the interposer, and the package. System simulation becomes an integral factor for the expected performance of the IC package.

Interposers act as a passive layer with a coefficient of thermal expansion that matches that of the chiplets, which explains the popularity of silicon for interposers. Nevertheless, it doesn’t eliminate the possibility of thermal hot spots and joule heating problems within the design. Interposers are supported by placing them on an ordinary substrate with a different thermal expansion coefficient, which contributes to increased mechanical stress and interposer warpage. That’s where the designer should be worried about the reliability of the system as this stress can easily crack some of the thousands of microbump connections.

Silicon interposers provide significantly denser I/O connectivity allowing higher bandwidth and better use of die space. But as we know, nothing comes for free. Multiple IPs in the same package require multiple power sources, constituting a complex power distribution network (PDN) within the package itself. The PDN runs throughout the entire package and is always vulnerable to power noise leading to power integrity problems. Analyzing the voltage distribution and current signature of every chip in the IC system with an interposer is important for ensuring power integrity.  Routing considerable amounts of power through the vertical connections between elements creates more problems for power integrity. These include TSVs and C4 bumps, as well as tiny micro-bumps, and hybrid bonding connections. Last but not least, many high-speed signals are routed among the chips and interposer which can easily fall victim to electromagnetic coupling and crosstalk. Electromagnetic signal integrity, also for high-speed digital signals, must be on your verification list when designing an IC package with interposer. This technology is a cost-effective, high-density, and power-efficient technique but is still susceptible to EM interference, thermal, signal and power integrity issues.

Power Integrity:  

Power is the most critical aspect of any IC package design. Everything around the package design is driven by the power consumed by chips within the IC package. Every chip has a different power requirement which leads to requirements for the power delivery network. The PDN also has a critical role in maintaining the power integrity of the IC package by minimizing voltage drop (IR-drop) and avoiding electromigration failures. The best way to achieve power integrity is to optimize the power delivery network by simulating the fluctuating current at each IC and the parasitic of passive elements that make up the PDN. It becomes more complicated with an interposer since chips are connected through the interposer. Power and ground trails routed through the interposer impose new challenges when analyzing power integrity. But it is not the only issue. Electromigration issues come hand in hand with PI problems. The current density in each piece of geometry must be modeled and should be below the maximum limit supplied by the foundry. Joule heating of the microbumps and wires has a significant impact on the maximum allowable current density, which implies a degree of thermal simulation for maximum accuracy.

Ansys Redhawk-SC and Totem, can extract the most accurate chip power model to understand the power behavior of chips in a full-system context. If you don’t yet have the chip layout model at the prototyping stage, create an estimated CPM (chip power model) using Ansys Redhawk tools to anticipate the physics at the initial level. Thermal and power analysis shouldn’t be a signoff step, but an ongoing process because making last-minute changes in the design might not work.

Thermal Integrity:  It is extremely important to understand the thermal distribution in the interposer design to regulate thermal integrity. Just power and signal integrity might not save your design from thermal runaway or local thermal failure. with multiple chips close together in a 2.5D package the hotter chiplet might heat up the nearby chiplets and change their power profile, possibly leading to yet more heating. Heat is dissipated from the chips to the interposer and further through TSVs to the substrate, which heats up the entire package. To avoid stress and warpage due to the differential thermal expansion, designers should understand the thermal profile of every chip and interposer in the design. These maps will give insight into the thermal distribution across the IC package, allowing the designer to determine thermal coupling among chips through the interposer.

Power dissipation is, of course, driven by activity. Ansys PowerArtist is an RTL power analysis tool that is integrated with in RedHawk-SC Electrothermal to generate the most accurate chip thermal models (CTMs) based on ultra-long, realistic activity vectors produced by hardware emulators. By assembling the entire 3D-IC system including chip CTM, interposer, package, and heat sink, Ansys RedHawk-SC Electrothermal gives the designer an accurate thermal distribution and an understanding of the thermal coupling between chiplets and the interposer. Monitoring temperature gradients needs to start early in the IC package design. The sooner the better. The complete front-to-back flow with gives a clear insight into the thermal distribution over time for the entire package, making your design more reliable.

Signal Integrity:  In the IC package, high-speed signals are transmitted from one die to another through an interposer at very high bit rates. The signals are closely spaced and also relatively long (compared to on-chip routing), which makes them vulnerable to electromagnetic interference (EMI) and coupling (EMC). Even digital designers need to follow high speed design guidelines to maintain signal integrity. The only way to control the EMC/EMI is with fast, high-capacity electromagnetic solvers that extract a coupled electromagnetic model including chiplets, signal routing through the interposer, and system coupling effect. With Ansys RaptorHand HFSS easy to analyze all these elements in a single, large model and meet the desired goal of a clean eye diagram. HFSS and Ansys Q3D can also be used to extract RLC parasitics and provide visualization of the electromagnetic fields and scale up to system level extraction beyond the interposer.

Learn more about challenges and solutions for 3D-IC and interposers.

Semiconductor Design and Simulation Software | Ansys

Ansys RedHawk-SC Electrothermal Datasheet

Thermal Integrity Challenges and Solutions of Silicon Interposer Design | Ansys

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