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Layout-based ESD Check Methodology with Fast, Full-chip Static and Macro-level Dynamic

Layout-based ESD Check Methodology with Fast, Full-chip Static and Macro-level Dynamic
by Daniel Payne on 05-22-2013 at 10:25 am

Nvidia designs some of the most powerful graphics chips and systems in the world, so I’m always eager to learn more about their IC design methodology. This week I’ve had the chance to talk with Ting Ku, Director of Engineering at Nvidia about his DAC talkin the Apache booth in exactly two weeks from today. Registration is required for this presentation.


Ting Ku, Nvidia


Interview

Q: What kind of SoC designs does your group work on?

Our VLSI team works on graphic and mobile processors.


Nvidia Fermi Block Diagram

Q: What is your role on the team?

My responsibilities are ESD design, circuit methodology, and SI methodology

Q: Tell me about your design challenges.

The biggest challenge is to design and implement work flows blessed by users that increases verification coverage. The topics can range from schedule tracker to automated analog layout creation.

Q: Which Apache tools are you using?

My team is using PathfinderStatic and Dynamic for full chip ESD check. We also use Totem to check electron migration and IR drop.

Q: How do the Apache tools fit into your overall EDA tool flows?

Today both tools fit in reasonably well since the tools allow many forms of entry. In both cases, the output of Apache tools is for human to review. So the integration of the tool is reasonably straight forward.

Q: How do the Apache tools help your design team?

The key benefit for Pathfinder check is coverage. Pathfinder was able to find power/ground rail mistakes that can cause ESD issues. The ability to see the full chip down to transistors is important. For Totem, the main benefits of this tool are in debug and capacity.


An Nvidia GPU Chip

Q: What other approaches did you try before using Apache tools?

We had a manual ESD review and a correct by construction approach, prior to Pathfinder. The result of such a manual method is really just hit and miss. Pathfinder + correct by construction have proven to be a very robust coverage combination for us. For EM/IR check, there are other tools like HSIM from Synopsys that does the same function. There are still people using HSIM in the company. For smaller designs, HSIM does a reasonable job. However, for larger designs, Totem shows the advantages in ease of debug, capacity, and run time.

Q: What was the learning curve like to become proficient with Apache tools?

Our learning curve was a bit painful on Apache tools in general. Some of the functions feel like patch work to me. This observation gives the indication that the tool was revised many times. Asking the whole team to become an expert in Apache’s tools is not realistic, so the best approach is to have an in-house automation layer to integrate the tool into the main work flow.

Q: What is support like from Apache?

Support is very reasonable from Apache. What I really like is that bug fixes and feature improvements come out very quickly. I would rank Apache’s response time on the top 25% of all the EDA vendors.

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