Power and Reliability Challenges

Last week I attended the Ansys/Apache seminars on “Dimensions of Electronic Design.” The two big challenges as we go down to 28nm and 20nm and below are keeping power manageable and keeping reliability up.

The big challenge with power is that we can put so much stuff on a die and clock it so fast that the power is exceeding the capability of batteries (which only increases slowly, not exponentially) and even exceeding thermal limits of either the package itself or the system (think smartphone).

Noise is another huge problem. With higher drive devices the average current may only increase slowly but the transient current is going up much faster. In turn this leads to inductive effect with fast changing currents. But as the supply voltage comes down we can’t scale the threshold voltage much (for leakage reasons) meaning that the noise margin reduces every process node, although FinFETs may give a one-time kick since they have better leakage characteristics.

Another thing I had not realized is that in 28nm and below a lot of signal lines need to be analyzed for electro-migration (EM) effects. A minimum width metal line with a high-powered buffer violates the EM constraints.

An integrated power-centric design methodology needs to start with RTL power analysis. Getting the architectural decisions right has a much bigger effect than anything that can be done later tweaking things during physical design. Going forward, one thing that will increasingly be important is whether or not to use 3D chips with TSVs. This can have a huge effect on timing and power (because the distances are so much shorter). Although there are inaccuracies at the RTL level, they are smaller than might be expected and, besides, waiting until gates are available is too late in the design cycle.

Later, once physical design is done, a full analysis can be performed. This can include a whole spectrum of tests that are becoming more and more important:

• off state leakage/voltage checks
• inrush current (powering up blocks)
• differential voltage checks
• time to rampup (power up blocks)
• noise coupling checks
• switch id-sat check

Finally, the speeds and noise sensitivity of everything means that the chip, package, system must all be analyzed together, including the whole power delivery network with decaps etc. There is not enough margin to analyze each part separately and the risks are that it is underdesigned (aka fails) or overdesigned (aka too costly). Of course, if this is a 2.5D (interposer) or 3D design then this will need to be a multi-die analysis.