3D Thermal Analysis

Matt Elmore of ANSYS/Apache has an interesting blog posting about thermal analysis in 3D integrated circuits. With both technical and economic challenges at process nodes as we push below 28nm, increasingly product groups are looking towards through-silicon-via (TSV) based approaches as a way of keeping Moore’s law on track and being able to deliver increasingly complex systems at acceptable cost.

There are lots of challenges with 3D ICs, from floorplanning, to noise, to power distribution, to test. But one of the big ones is thermal analysis. Once you stack a lot of die on top of each other, heat from the silicon in the center can really only be dissipated by through the other die. The TSVs themselves, which are large copper plugs (well, large by semiconductor standards), are not just an electrical interconnect between adjacent die but also a thermal connection. Heat from the center is moved in the vertical axis, which with care can be a very good thing. The biggest area where care needs to be taken is to ensure that hot spots on one die do not align with hot spots on the die above or below. The big risk here is thermal runaway, where the temperature increase in turn increases current and power and so further increases the temperature. A chip can be completely destroyed by this.

Temperature affects performance, reliability, stress and leakage. So a full analysis of a 3D design is not straightforward since everything affects everything else. In particular, temperature affects performance and performance affects temperature.

A good analysis needs a model of how the temperature affects other aspects of the design at micron resolution. In turn this needs to interact with models of the chip, package and board to arrive at a sort of “thermal closure”.

Read the blog posting here.