Constrain all you want, we’ll solve more

EDA tool development is always pushing the boundaries, driven in part by bigger, faster chips and more complex IP. For several years now, the trend has been developing tools that spot problems faster without waiting for the “big bang” synthesis result that takes hours and hours. Vendors, with help from customers, are tuning tools to real-world results.

Such is the case with Aldec and Riviera-PRO, their functional verification environment. I asked Dmitry Melnik, product manager for Aldec, to provide an overview of the thinking behind the latest release, Riviera-PRO 2013.06. His response shows the advantages of working with a more nimble organization like Aldec, able to team with lead customers who have seen the value in a tool but want to continue improving the efficiency of their design flow.

One of the bigger breakthroughs Melnik points to is improved simulation speeds with full coverage enabled. The performance data shows this latest release speeds up statement & branch coverage 3x, and expression coverage 1.5x in SystemVerilog designs. Asking how Aldec achieved this, Melnik said they are looking at what customers are actually doing with the tool, profiling the operations in the simulator, and recoding the bottlenecks accordingly. That sounds obvious, but until a picture of real-world usage develops with large designs in play, it isn’t.

Aldec teams also tuned Riviera-PRO simulation performance on Linux platforms, leading to an average 10% overall performance increase, and up to 20% in SystemC simulation and some scenarios of assertions and trace. In this release, Windows 8 support is also official.

Also included in the release is a Classes window, presenting SystemVerilog classes in a hierarchical tree view. This avoids the tedious process of digging through code to follow inheritance and find the base class, then matching the names across modules. Melnik says that is an important feature now being provided industry-wide in most verification tools, and gives customers another productivity boost.

If one only reads the press release for Riviera-PRO 2013.06, these features might appear to be all the news. In fact, probably the biggest feature of this new release is an all-new SystemVerilog constraint solver. As we’ve written about before, constrained randomization is a key technique in many verification strategies, particularly UVM – and this release includes the latest UVM 1.1d library. However, constraint solvers are a scientific-class compute problem of epic proportions, and a less-than-good solver can take forever to produce results.

With more a bit of modesty, Melnik finally admitted that this release includes a ground-up rewrite of the constraint solver – involving about a year of work. “Like many of the bigger EDA companies, we have a dedicated team working full time on the constraint solver,” he said. Another observation is a lesson learned over the course of customer engagements with Riviera-PRO: “Not all constraints are equal. Customers have to be smart about how constraints are written; avoiding or rewriting problematic constraints leads to faster closure.”

The bottom line is the claims aren’t just puffing based on some artificial benchmarking scenarios. Aldec is investing heavily in customer-driven improvements to Riviera-PRO, developing a deeper understanding of real-world problems and how to be more efficient in design verification.

You can read more of Melnik’s thoughts in the Aldec blog, including his DAC 2013 insights.

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