Cadence Increases Verification Efficiency up to 5X with Xcelium ML

Cadence Increases Verification Efficiency up to 5X with Xcelium ML
by Mike Gianfagna on 08-13-2020 at 6:00 am

Screen Shot 2020 08 07 at 11.24.49 PM

SoC verification has always been an interesting topic for me. Having worked at companies like Zycad that offered hardware accelerators for logic and fault simulation, the concept of reducing the time needed to verify a complex SoC has occupied a lot of my thoughts. The bar we always tried to clear was actually simple to articulate… Read More


Effective Verification Coverage through UVM & MDV

Effective Verification Coverage through UVM & MDV
by Pawan Fangaria on 03-10-2014 at 5:00 pm

In the current semiconductor design landscape, the design size and complexity of SoCs has grown to large extent with stable tools and technologies that can take care of integrating several IPs together. With that mammoth growth in designs, verification flows are evolving continuously to tackle the verification challenges … Read More


Constrain all you want, we’ll solve more

Constrain all you want, we’ll solve more
by Don Dingee on 07-24-2013 at 8:30 pm

EDA tool development is always pushing the boundaries, driven in part by bigger, faster chips and more complex IP. For several years now, the trend has been developing tools that spot problems faster without waiting for the “big bang” synthesis result that takes hours and hours. Vendors, with help from customers, are tuning tools… Read More


A random walk down OS-VVM

A random walk down OS-VVM
by Don Dingee on 05-13-2013 at 11:14 am

Unlike one prevailing theory of financial markets, digital designs definitely don’t function or evolve randomly. But many engineers have bought into the theory that designs can be completely tested randomly. Certainly there is value to randomness, exercising all combinations of inputs, including unexpected ones a designer… Read More