In the current semiconductor design landscape, the design size and complexity of SoCs has grown to large extent with stable tools and technologies that can take care of integrating several IPs together. With that mammoth growth in designs, verification flows are evolving continuously to tackle the verification challenges at various levels. Today, verification is not a single continuous flow; it is being done from several different angles including formal verification; h/w, s/w and h/w-s/w co-simulation; acceleration, emulation, assertion-based and so on. VIPs (Verification IPs) for standard components in SoCs are to the fore to ease the pressure on verification teams.
In such a scenario, it’s evident that the verification of SoCs in every organization must be a continuous improvement and coverage building process where coverage from various verification processes can be added up and accumulated; testcases, testbenches and verification plans maintained and re-used between same as well as different projects to the largest extent possible; interoperability maintained between different verification engines and best quality obtained with optimum utilization of resources.
Cadencehas established a very novel, effective and everlasting methodology for verification called MDV (Metric-driven Verification) that uses the well-known standard UVM (Universal Verification Methodology) which is based on OVM (Open Verilog Methodology), itself an evolution from eRM (e Reuse Methodology). UVM supports both e and SystemVerilog, thus enjoying wide-spread use in the semiconductor industry.
MDV methodology advocates a step-by-step approach in a planned way starting from test coverage, code coverage, advanced verification up to planned verification closure of design features. Cadence Incisive Verification Kit includes verification planning (test structures against specific features can be specified in MS Excel spread sheet) codified within the tool. The vPlanner feature of Incisive vManager can also be used to identify abstract features and hierarchies of features that closely resemble the hierarchy of specification. A vPlan can be hierarchical integrating together vPlans of other features. It becomes executable when it is able to re-direct verification activities and is dynamically updated with highest priority items executed first. The coverage is accumulated progressively as various verification engines execute. Test driven verification is RTL centric and can be in the form of block, expression, toggle or finite state machine coverage. Then there is additional assertion-based functional testing. Constrained Random testing, although incapable of keeping track of what is tested, is very effective in finding bugs in random manner. The tracking and visualization of what has been tested is done by Coverage Driven approach; however that can generate huge data, thus limiting usability and scalability. In a generic approach of plan-based MDV, the overall verification can be organized in a verification plan which can have milestones set, feature wise or design hierarchy wise, and can capture what is tested through various means; feature hierarchies are organized by the executable vPlan which contains many-to-many relationships between features and tests, thus also helping in traceability against specification.
Incisive Verification Kit includes several real world testbench examples that can enable design verification engineers to plan and embrace this new verification methodology and scale on productivity through re-use of verification plans, testbenches and several other components. Above is a testbench architecture that shows how UVCs (Universal Verification Components) are hooked up together to a UART DUT. Then there is a cluster-level testbench for the kit APB system with major re-use of serial interface and APB UVCs. This modular and layered approach creates a user-friendly plug-and-play environment where hardware and software verification components can be easily re-used from block to cluster to chip to system between multiple projects and platforms. Each of these components has its own pre-defined executable vPlan which can be plugged into the master vPlan of the SoC. Cadence has a rich set of commercial VIPs for standard interfaces (e.g. USB, PCI Express, AXI etc.) in its portfolio.
The intensity of re-use in this verification platform plays a vital role in accelerating the testbench development and scaling verification for large SoCs through manageable, repeatable and closed-loop process. Not only are the verification components re-used, but also vPlans, sequence libraries and register definitions.
MDV provides analysis of coverage contribution for each regression run against a specific feature. Random seeds and tests that contribute most to the overall coverage can be identified and run as much of the time as possible for effective simulations.
It’s interesting to note the results from a real Cadence customer project where project timeframe was reduced from 12 months to 5 months and more bugs found with lesser resources.
The Incisive Verification Kitprovides comprehensive hands-on workshops (which include techniques from both planning and execution perspectives) for verification engineers getting up to speed with MDV platform. It has material for several design paradigms such as low-power and mixed-signal. A subset of the workshops is available through Cadence online support in Cadence Rapid Adoption Kits. Read the Cadence whitepaper for more detailed description on this powerful and effective SoC verification methodology.