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TRNG for Automotive achieves ISO 26262 and ISO/SAE 21434 compliance

TRNG for Automotive achieves ISO 26262 and ISO/SAE 21434 compliance
by Don Dingee on 02-27-2025 at 6:00 am

Synopsys Automotive NIST TRNG

The security of a device or system depends mainly on being unable to infer or guess an alphanumeric code needed to gain access to it or its data, be that a password or an encryption key. In automotive applications, the security requirement goes one step further – an attacker may not gain access per se, but if they can compromise vehicle… Read More


Synopsys Expands Hardware-Assisted Verification Portfolio to Address Growing Chip Complexity

Synopsys Expands Hardware-Assisted Verification Portfolio to Address Growing Chip Complexity
by Kalar Rajendiran on 02-25-2025 at 6:00 am

Synopsys HAV Product Family

Last week, Synopsys announced an expansion of their Hardware-Assisted Verification (HAV) portfolio to accelerate semiconductor design innovations. These advancements are designed to meet the increasing demands of semiconductor complexity, enabling faster and more efficient verification across software and hardware… Read More


How Synopsys Enables Gen AI on the Edge

How Synopsys Enables Gen AI on the Edge
by Mike Gianfagna on 02-24-2025 at 10:00 am

How Synopsys Enables Gen AI on the Edge

Artificial intelligence and machine learning have undergone incredible changes over the past decade or so. We’ve witnessed the rise of convolutional neural networks and recurrent neural networks. More recently, the rise of generative AI and transformers. At every step, accuracy has been improved as depicted in the graphic… Read More


Synopsys Expands Optical Interfaces at DesignCon

Synopsys Expands Optical Interfaces at DesignCon
by Mike Gianfagna on 02-17-2025 at 6:00 am

Synopsys Expands Optical Interfaces at DesignCon

The exponential growth of cloud data centers is well-known. Driven by the demands of massive applications like generative AI, state-of-the-art data centers present substantial challenges in terms of power consumption. And AI is poised to drive a 160% increase in data center power demand while also increasing demands on storage… Read More


What is Different About Synopsys’ Comprehensive, Scalable Solution for Fast Heterogeneous Integration

What is Different About Synopsys’ Comprehensive, Scalable Solution for Fast Heterogeneous Integration
by Mike Gianfagna on 02-03-2025 at 10:00 am

What is Different About Synopsys’ Comprehensive, Scalable Solution for Fast Heterogeneous Integration

Multi-die design has become the center of a lot of conversation lately. The ability to integrate multiple heterogeneous devices into a single package has changed the semiconductor landscape, permanently. This technology has opened a path for continued Moore’s Law scaling at the system level. What comes next will truly be exciting.… Read More


Will 50% of New High Performance Computing (HPC) Chip Designs be Multi-Die in 2025?

Will 50% of New High Performance Computing (HPC) Chip Designs be Multi-Die in 2025?
by Kalar Rajendiran on 01-28-2025 at 6:00 am

Synopsys Predictions for Multi Die Designs in 2025

Predictions in technology adoption often hinge on a delicate balance between technical feasibility and market dynamics. While business considerations play a pivotal role, the technical category reasons for the success or failure of a prediction are more tangible and often easier to identify—if scrutinized with care. However,… Read More


A Deep Dive into SoC Performance Analysis: Optimizing SoC Design Performance Via Hardware-Assisted Verification Platforms

A Deep Dive into SoC Performance Analysis: Optimizing SoC Design Performance Via Hardware-Assisted Verification Platforms
by Lauro Rizzatti on 01-22-2025 at 10:00 am

A Deep Dive into SoC Performance Analysis Part 2 Figure 1

Part 2 of 2 – Performance Validation Across Hardware Blocks and Firmware in SoC Designs

Part 2 explores the performance validation process across hardware blocks and firmware in System-on-Chip (SoC) designs, emphasizing the critical role of Hardware-Assisted Verification (HAV) platforms. It outlines the validation workflowRead More


Synopsys Brings Embedded Memory to the Future with its Flexible, IP-Based Compilers

Synopsys Brings Embedded Memory to the Future with its Flexible, IP-Based Compilers
by Mike Gianfagna on 01-20-2025 at 6:00 am

Synopsys Brings Embedded Memory to the Future with its Flexible, IP Based Compilers

There is a revolution happening that is fueled by innovation in areas such as AI, IoT and autonomous driving. These new systems put incredible stress on next-generation semiconductor technology. Faster processing, higher density and lower latency must all be delivered with reduced power and thermal profiles. One technology… Read More


A Deep Dive into SoC Performance Analysis: What, Why, and How

A Deep Dive into SoC Performance Analysis: What, Why, and How
by Lauro Rizzatti on 01-15-2025 at 6:00 am

A Deep Dive into SoC Performance Analysis Part 1 Figure 2

Part 1 of 2 – Essential Performance Metrics to Validate SoC Performance Analysis

Part 1 provides an overview of the key performance metrics across three foundational blocks of System-on-Chip (SoC) designs that are vital for success in the rapidly evolving semiconductor industry and presents a holistic approach to optimizeRead More


Ultra Ethernet and UALink IP solutions scale AI clusters

Ultra Ethernet and UALink IP solutions scale AI clusters
by Don Dingee on 12-19-2024 at 6:00 am

UALink and Ultra Ethernet roles in AI infrastructure clusters

AI infrastructure requirements are booming. Larger AI models carry hefty training loads and inference latency requirements, driving an urgent need to scale AI acceleration clusters in data centers. Advanced GPUs and NPUs offer solutions for the computational load. However, insufficient bandwidth or latency between servers… Read More