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FPGA
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Know what 5G is? You’re probably wrong

Know what 5G is? You’re probably wrong
by Tom Simon on 07-12-2018 at 12:00 pm
Categories: 5G, Achronix, Automotive, eFPGA, FPGA, IoT, Mobile

If you think the transition to 5G will be anything like the transitions before it to 3G or 4G, you are in for a big surprise. Not only will the transition take longer than either of the previous transitions, its ramifications will spread far beyond cell phones and into other areas such as automobiles, AI, healthcare, and commerce. … Read More

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When Why and How Should You Use Embedded FPGA Technology

When Why and How Should You Use Embedded FPGA Technology
by Alok Sanghavi on 06-27-2018 at 7:00 am
Categories: Achronix, eFPGA, FPGA

If integrating an embedded FPGA (eFPGA) into your ASIC or SoC design strikes you as odd, it shouldn’t. ICs have been absorbing almost every component on a circuit board for decades, starting with transistors, resistors, and capacitors — then progressing to gates, ALUs, microprocessors, and memories. FPGAs are simply one more… Read More

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When FPGA Design Looks More Like ASIC Design

When FPGA Design Looks More Like ASIC Design
by Bernard Murphy on 06-08-2018 at 7:00 am
Categories: EDA, FPGA, Synopsys

I am sure there are many FPGA designers who are quite content to rely on hardware vendor tools to define, check, implement and burn their FPGAs, and who prefer to test in-system to validate functionality. But that approach is unlikely to work when you’re building on the big SoC platforms – Zynq, Arria and even the big non-SoC devices.… Read More

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Block RAM integration for an Embedded FPGA

Block RAM integration for an Embedded FPGA
by Tom Dillinger on 05-22-2018 at 12:00 pm
Categories: eFPGA, Flex Logix, FPGA, IP
2 Comments

The upcoming Design Automation Conference in San Francisco includes a very interesting session –“Has the Time for Embedded FPGA Come at Last?” Periodically, I’ve been having coffee with the team at Flex Logix, to get their perspective on this very question – specifically, to learn about the key features that customers are seeking… Read More

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Hard IP for an embedded FPGA

Hard IP for an embedded FPGA
by Tom Dillinger on 04-30-2018 at 12:00 pm
Categories: eFPGA, Flex Logix, FPGA, IP
1 Comment

As Moore’s Law enables increased integration, the diversity of functionality in SoC designs has grown. Design teams are seeking to utilize outside technical expertise in key functional areas, and to accelerate their productivity by re-using existing designs that others have developed. The Intellectual Property (IP) industry… Read More

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Achronix Momentum Building with Revenue Growth, Product/Staff Expansion, New HQ

Achronix Momentum Building with Revenue Growth, Product/Staff Expansion, New HQ
by Camille Kokozaki on 04-27-2018 at 7:00 am
Categories: Achronix, eFPGA, FPGA

5G Wireless, Network Acceleration, Data centers, Machine Learning, Compression, Encryption fueling the Growth

Building on its increasing momentum, Achronix Semiconductor Corporation held a ribbon-cutting ceremony on Tuesday, April 25, with the presence of Santa Clara’s Mayor Lisa Gillmor, customers, and partners, employees… Read More

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RDC – A Cousin To CDC

RDC – A Cousin To CDC
by Alex Tan on 04-18-2018 at 12:00 pm
Categories: Aldec, EDA, FPGA

In a post-silicon bringup, it is customary to bring the design into a known state prior to applying further testing sequences. This is achieved through a Power-on-Reset (POR) or similar reset strategy which translates to initializing all the storage elements to a known state.

During design implementation, varying degrees of… Read More

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The 4th Way Beyond Simulation, FPGA Synthesis, and Emulation

The 4th Way Beyond Simulation, FPGA Synthesis, and Emulation
by Camille Kokozaki on 04-06-2018 at 7:00 am
Categories: EDA, FPGA

As verification continues to be a key ingredient in successful design implementation, new approaches have been tried to balance cost, time to results and comprehensive analysis in designs that require large patterns in some application like Image Processing. Simulation environments are well proven, and designers tend to … Read More

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FPGA, Data and CASPA: Spring into AI (2 of 2)

FPGA, Data and CASPA: Spring into AI (2 of 2)
by Alex Tan on 03-23-2018 at 12:00 pm
Categories: AI, CASPA, EDA, FPGA, Intel Foundry, SiFive, Xilinx

Adding color to the talks, Dr. Jeff Welser, VP and IBM Almaden Research Lab Director showed how AI and recent computing resources could be harnessed to contain data explosion. Unstructured data growth by 2020 would be in the order of 50 Zetta-bytes (with 21 zeros). One example, the Summit supercomputer developed by IBM for use at… Read More