As I have written before, IoT looks to be a key driver for design starts and future semiconductor revenue growth which is why we wrote “PROTOTYPICAL” and included a field guide to FPGA Prototyping. If you want to get funding for your new IoT chip project, having a working prototype is a good thing, absolutely. If you want to take a look… Read More
Power Noise Sign-off at #53DAC
When I hear the company name of ANSYS the first EDA tool category that comes to mind is power noise sign-off. Going to DAC is a great way to find out what’s new with EDA, IP and foundries. There are three places that you can find ANSYS at DAC this year:… Read More
"Re-Inventing" Tapeout Sign-off — Applying Big Data Techniques to Electrical Analysis
A common SoC design methodology in current use starts with preparation of the physical floorplan — e.g., block/pin placement, global clock domain and bus signal planning, developing the global/local power distribution (and dynamic power domain management techniques). Decoupling capacitor estimated densities and… Read More
Rebooting EDA
In the 35 years since commercial EDA went mainstream a lot of advances have been made but the fundamental architecture and even the philosophy of tooling have really not advanced at all. Tools are designed around individual tasks – analysis and optimization within a specific domain – under the assumption that variability within… Read More
FinFETs, Power Integrity and Chip/Package Co-design
FinFETs have brought a lot of good things to design – higher performance, higher density and lower leakage power – promising to extend Moore’s law for a least a while longer. But inevitably with new advances come new challenges, especially around optimizing for power integrity in these designs.
One of these challenges is… Read More
Early Structural Reliability Analysis of a Chip-Package-System design is a must!
2015 will be remembered as the year when chip-package-system (CPS) physical co-design and electrical/thermal analysis methodologies took center stage.… Read More
A Synergistic Chip-Package-System Analysis Methodology
Looking back, 2015 was a significant year for mergers and acquisitions in the EDA industry. The Semiwiki team maintains a chronology of major transactions here.
As I was reviewing this compendium, one of the entries that stands out is the acquisition of Apache Design Solutions by Ansys, Inc. a couple of years ago.
At that time, there… Read More
Simulating Full-System EMI for a Car in Just 28 Minutes
While there’s a lot of cool technology in modern semiconductors, it’s important to raise our sights periodically to understand how well these chips will work in the systems for which they are designed. One area driving a lot of semiconductor growth is automobile electronics. We’ve had drive-train control forever it seems, but… Read More
Electromigration Analysis and FinFET Self-Heating
FinFET processes provide power, performance, and area benefits over planar technologies. Yet, a vexing problem aggravated by FinFET’s is the greater local device current density, which translates to an increased concern for signal and power rail metal electromigration reliability failures. There is a critical secondary… Read More
Why You Really Need Chip-Package Co-analysis
There’s only one software company that I know of that covers four major disciplines: Fluids, Structures, Electronics and Systems. That company is ANSYS and when they acquired Apache Design Automation back in 2011 they filled out their products for electronics design, and more specifically in the area of integrated chip-package… Read More