Author: Daniel Payne

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What Applications Implement Best with High Level Synthesis?

What Applications Implement Best with High Level Synthesis?
by Daniel Payne on 07-26-2013 at 3:12 pm
Categories: EDA

RTL coding using languages like Verilog and VHDL have been around since the 1980’s and for almost as long a time we’ve been hearing about High Level Synthesis, or HLS that allows an SoC designer to code above the RTL level where you code at the algorithm level. The most popular HLS languages today are C, C++ and SystemC.… Read More

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Mixed Signal SOC verification Webinar

Mixed Signal SOC verification Webinar
by Daniel Payne on 07-16-2013 at 8:29 pm
Categories: Concept Engineering, EDA

When looking at the time to design and verify an SoC we’ve known for many years now that the verification effort requires more time than the design process. So anything that will shorten the verification effort will have the biggest impact on keeping your project on schedule.

A second trend is the amount of Analog content in… Read More

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Minimize the Cost of Testing ARM® Processor-based Designs and Other Multicore SoCs

Minimize the Cost of Testing ARM® Processor-based Designs and Other Multicore SoCs
by Daniel Payne on 07-15-2013 at 1:37 pm
Categories: EDA, FPGA, Synopsys

On my first job out of college as an IC design engineer I was surprised to discover that a major cost of chips was in the amount of time spent on the tester before being shipped. That is still true today, so how would you keep your tester time down, test coverage high and with a minimum number of pins when using multiple processors on a single… Read More

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Best Practices for Using DRC, LVS and Parasitic Extraction – on YouTube

Best Practices for Using DRC, LVS and Parasitic Extraction – on YouTube
by Daniel Payne on 07-10-2013 at 1:21 pm
Categories: EDA

EDA companies produce a wealth of content to help IC engineers get the best out of their tools through several means:

  • Reference Manuals
  • User Guides
  • Tutorials
  • Workshops
  • Seminars
  • Training Classes
  • Phone Support
  • AE visits
… Read More
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Full Chip IR Drop Analysis using Distributed Multi Processing

Full Chip IR Drop Analysis using Distributed Multi Processing
by Daniel Payne on 07-02-2013 at 6:56 pm
Categories: Ansys, Inc., EDA

IR drop analysis across your board, package and SoC ensures that your Power Delivery Network (PDN) is robust, and that your system will function to spec. There are both static and dynamic approaches to IR drop analysis of a full-chip with billions of transistors, while the dynamic approach produces the most accurate results compared… Read More

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Design Test and Regression Management of SoCs

Design Test and Regression Management of SoCs
by Daniel Payne on 06-28-2013 at 2:26 pm
Categories: EDA, Perforce

Eric Peersfounded Missing Link tools in 2008 and his company was acquiredby Methodics in 2012, so I met with him at DAC to understand how their EDA tools for Design, Test and Regression Management are used in an SoC design.


Eric Peers, Methodics… Read More