WP_Term Object
(
    [term_id] => 34
    [name] => Ansys, Inc.
    [slug] => ansys-inc
    [term_group] => 0
    [term_taxonomy_id] => 34
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 256
    [filter] => raw
    [cat_ID] => 34
    [category_count] => 256
    [category_description] => 
    [cat_name] => Ansys, Inc.
    [category_nicename] => ansys-inc
    [category_parent] => 157
)
            
ansys sim world 2024 800X100 reg a (1)
WP_Term Object
(
    [term_id] => 34
    [name] => Ansys, Inc.
    [slug] => ansys-inc
    [term_group] => 0
    [term_taxonomy_id] => 34
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 256
    [filter] => raw
    [cat_ID] => 34
    [category_count] => 256
    [category_description] => 
    [cat_name] => Ansys, Inc.
    [category_nicename] => ansys-inc
    [category_parent] => 157
)

Low-Power Design Analysis and Optimization for Mobile and High-Performance Computing Applications

Low-Power Design Analysis and Optimization for Mobile and High-Performance Computing Applications
by Daniel Payne on 08-23-2013 at 7:36 pm

For several decades now consumers like me have enjoyed using mobile devices including:

  • Transistor radios, my first one had just 6 discreet transistors in the 1960’s
  • HP 21 Calculator, used in college with Reverse Polish Notation, circa 1976
  • Zenith Data Systems laptop, with two floppy drives, 1980’s
  • Palm Pilot V, a useful PDA before smart phones that is, 1990’s

Fast forward to today where I enjoy using mobile devices with up to billions of transistors:

  • MacBook Pro 17″ with 16GB of RAM, and an Intel Quad Core i7 processor
  • iPad 3 with 16GB of Flash, and A5X quad-core ARM processor
  • Samsung Galaxy Note II with 5.5″ display, powered by a quad-core Cortex-A9 processor


We have grown very accustomed to new generation devices that have faster performance, lower power and run longer on a single battery charge. These three general trends place a daunting challenge on SoC and electronic system designers. Fortunately there is some help in sight by using EDA tools that can:

  • Measure power at the chip, package and board levels at the earliest point in your design process to see if you will meet the target specifications
  • Verify power integrity for sub 1 V supply levels for the many modes of your SoCs
  • Simulate all of your high-speed low-power I/Os, like LPDDRs to verify they work in the presence of core and system noise within your jitter specs
  • Perform checks for Electromigration (EM) and Electrostatic Discharge (ESD) to ensure a long product life
  • Run thermal simulations to see how stable your electronic design really is


Apache Ultra Low Power Flow

There’s a webinar hosted by ANSYS-Apache on Tuesday, August 27th that will address these specific types of analysis, starting at 4PM EDT or 8PM GMT. Registration is required so sign-up here.

You will hear about how to design mobile and high-performance ICs for power and reliability using the simulation platforms engineered by ANSYS-Apache. The webinar will last 60 minutes, is free, and you’ll have a chance to ask questions about how the Apache tools work.

lang: en_US

Share this post via:

Comments

0 Replies to “Low-Power Design Analysis and Optimization for Mobile and High-Performance Computing Applications”

You must register or log in to view/post comments.