There was a lot to learn at the TSMC Technical Symposium last week, in the keynotes for sure but also in the halls and exhibits. Tom Dillinger did a nice job covering the keynotes in his posts Key Take aways from the TSMC Technology Symposium Part 1 and Part 2 but there was something interesting that many people may have missed in the exhibit… Read More
Author: Daniel Nenni
TSMC and ARM Serving up 7nm!
One thing I learned while writing the books about TSMC and ARM is that collaboration has always been at the core of both companies. They started with collaboration on day one and it is now a natural part of their business models. And the word collaboration in the fabless semiconductor ecosystem gets redefined at every process node,… Read More
Mentor Extends Verification Offering!
With verification consuming more and more of the design cycle and the increasingly complex industry standard interfaces that are now common place, Verification IP (VIP) is again a trending topic. Back in my IP days the age old question was: Is it better to use VIP from the IP vendor? Because you know it will work, right? Or is it better… Read More
Where is the Money in IoT?
As we all know IoT (Internet of Things) is the “next big thing” across many different industries including the fabless semiconductor ecosystem. The first recorded IoT blog on SemiWiki was in 2014 and currently we have 173 IoT blogs posted that have earned more than 600,000 views and counting. So yes, IoT is the next big thing, absolutely.… Read More
Cadence is again the best EDA company to work for!
We wrote about the history of Cadence in preparation for our book “Fabless: The Transformation of the Semiconductor Industry” in 2012. EDA played a key role in enabling the fabless semiconductor revolution and Cadence was right there at the beginning. Famed EETimes editor Richard Goering helped us with the book and the Cadence… Read More
TSMC 2016 Technology Symposium and Apple SoCs!
It is that time again, time for the originators of the pure-play foundry business to update their top customers and partners on the latest process technology developments and schedules. More specifically, all of the TSMC FinFET processes (16nm, 10nm, 7nm, and beyond), TSMC IP portfolio (CMOS image sensor, Embedded Flash, Power… Read More
Dr. Walden Rhines on the Past Present and Future!
Who can present seventy six slides in sixty minutes, still have time for questions, AND make it interesting? Dr. Walden Rhines that’s who. Here is a link to the presentation but I have to warn you, it is a 100MB PDF file:
Design Verification Challenges: Past, Present, and Future
The DVCon conference was well attended again this year… Read More
Start Your HBM 2.5D Design Today!
Next week there is a live seminar at the famed Computer Museum in Silicon Valley that you won’t want to miss. If you haven’t been to the Computer Museum here is what you are missing:… Read More
Solving the Next Big SoC Challenges with FPGA Prototyping
The health of the semiconductor industry revolves around the “start”. Chip design starts translate to wafer starts, and both support customer design wins and product shipments. Roadmaps develop for expanding product offerings, and capital expenditures flow in to add capacity enabling more chip designs and wafer starts. If… Read More
Design Verification Challenges: Past, Present and Future!
Next week I will be at DVCON which is not to be confused with DEFCON the community of black and white hat hackers that challenge our online privacy on a daily basis. DVCON is the premier conference for the functional design and verification of our beloved electronic devices. The big draw next week of course is the keynote by Dr. Walden… Read More
Rapidus, IBM, and the Billion-Dollar Silicon Sovereignty Bet