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FD-SOI, FinFET, 3D in Monterey

FD-SOI, FinFET, 3D in Monterey
by Paul McLellan on 04-09-2014 at 5:40 pm

Last night the IEEE Silicon Valley Chapter had a panel session that was in some ways a preview of some of what will be discussed at the Electronic Design Process Symposium in Monterey next Thursday and Friday. At EDPS Herb Reiter organized a session on FinFET, 3DIC and FD-SOI (sort of how many buzzwords can you get into one set of titles). Apparently I drew the short straw since I get the last presentation of the day, the one between everyone and a glass of wine and dinner, and a dinner keynote by Wally Rhines (who coincidentally sat next to me at lunch just a couple of hours ago).

 I am talking about FD-SOI. So I got asked to present FD-SOI since it is the only alternative to FinFET that is out there. Unfortunately ST is the only company driving the technology and building the ecosystem (mainly wafer blanks) required. GlobalFoundries announced that they would have FD-SOI as well as FinFET but…that seems no longer to be the case.

I think of FD-SOI and FinFETs as being two solutions to the same problem, namely that in bulk CMOS the gate no longer strongly controls the channel so all the transistors are never completely off. This is why leakage power became such a big problem in recent nodes. The solution is to make the channel thin and the two ways to do this are to make it a thin vertical fin (and then wrap the gate around 3 sides for even better control) or to make the channel horizontally but thin by backing it up with an insulator (so no current can get around the channel since an insulator won’t let current flow).


Conveniently for me, Handel Jones of IBS, just came out with a report where he and his people have done an analysis of the costs of FinFET vs FD-SOI which comes out strongly in favor of FD-SOI. At 14nm/16nm there is a cost saving using FD-SOI of nearly 30% versus bulk FinFET.

The challenge, of course, is whether any high-volume customer will step up and demand this cost-saving. Instead, the expectation is that the high volume of FinFETs will lead to more yield learning than lower volume FD-SOI so that this will eventually be eroded.

Apart from Wally Rhines dinner keynote, the opening keynote on Thursday is by Chris Lawless of Intel and the opening keynote on Friday is Martin Lund of Cadence.

I will have a lot more to say next week. Details of the agenda are here. Registration is here. Get a $50 discount by using the code semiwikigo. I hope to see you there.


More articles by Paul McLellan…


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