I spent the morning at Mentor where they announced their new enterprise verification platform. This was a general announcement but was attended by a lot of the international press who were over on a GlobalPress tour (the event that used to take up camp at Chaminade).
But first Wally Rhines spent 30 minutes giving a nice overview of the history of verification, building up to the fact that this announcement is really verification 3.0, with a unified environment for simulation, emulation and formal with support for both hardware and software debugging. The big word is “common”: common debug, common verification IP, common user interface, common testbench stimulus, common assertions and common coverage. He passed the reins to John Lenyo, who is the general manager of verification to go over the details.
There are actually four new platform components:
- new emulation operating system: Veloce OS3
- new high-performance, unified HW debugger: Visualizer
- new unified software debugger: Codelink
- new verification IP (VIP) that supports Questa and Veloce
The underlying engines remain unchanged: Vista Virtual Prototype, the Questa Formal and Questa Simulation engines, and Veloce emulation.
The new emulation operating system allows emulators to deliver simulation-like capabilities. It replaces hardware add-ons with virtual peripherals. It simplifies configuration. The result is that Veloce can be configured and run from anywhere on the network and so it can be moved into the data-center. Note that there is no new emulator, just a new operating system. It is backwards compatible and runs on all old Veloce systems, the biggest of which have a capacity of 1B gates (and two of these can be linked to get to 2B). The result is that it is much more straightforward to bring up a design for emulation (no playing with cables). It supports UPF for power verification, SystemVerilog for functional coverage and assertion-based verification and SystemVerilog, UVM and C/C++ testbenches. All the coverage metrics are captured into the single coverage database shared with the other engines called UDCB.
Visualizer is a new high-performance high-capacity debugger (for hardware). All verification engines share the same debugger. Of course it has full tandads support and also supports different abstraction levels: transaction and protocol debug, performance and system-level analysis and HW/SW system debug.
For software development there is a new debugger Codelink that runs on both Questa and Veloce OS3. It allows software debug to be done on a shared Veloce emulator (of course there have to be enough gates for all the designs). It can handle up to about 10 simultaneous users.
Finally, the existing VIP that Mentor has is all moved so that it fully supports both Questa and Veloce. This gives testbench portability across simulation and emulation, common validation/QA tests and a common user tesetbench and device-under-test (DUT) interface.
Although they weren’t announcing anything today, John hinted at announcements coming in the next 12 months extending the enterprise verification platform with its unified debuggers and databases to FPGA prototypes, first silicon, production test and even fielded product.
After the presentation we were taken to their server room where they have several Veloce emulators. These are used for evaluations, Mentor doesn’t provide an emulation service. Then lunch.